An Ultrawide Load-Range Fast-Transient Output Capacitor-Less Digital LDO With Adaptive Gate Modulation and Droop Detection

IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Solid-State Circuits Letters Pub Date : 2024-06-27 DOI:10.1109/LSSC.2024.3420117

Gunmo Koo;Jaejin Kim;Seongmin Lee;Jae Hoon Shim;Kunhee Cho

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引用次数: 0

Abstract

An ultrawide load-range output capacitor-less digital LDO (DLDO) with an adaptive gate modulation scheme is described. The proposed DLDO is primarily regulated by digital codes with a synchronous clock signal while the gate driving level is dynamically adjusted according to the load current level. The proposed gate modulation scheme can significantly widen the dynamic range of load current and reduce the output voltage ripple. In addition, an asynchronous droop detection circuit, coupled with adaptive gate modulation, is added to improve the voltage droop and ensure fast recovery from load transients. The proposed DLDO was fabricated in 28-nm CMOS process. The dynamic load range of 57

$143\times $

(1.4–

$80~\mu $

A) is achieved and the output voltage ripple of under 17 mV is measured across the entire load current range. A response time of less than 10 ns and a recovery time of less than 30 ns are measured in various load transient conditions.

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具有自适应栅极调制和下拉检测功能的超宽负载范围快速瞬态输出无电容数字 LDO

本文介绍了一种采用自适应栅极调制方案的超宽负载范围输出无电容数字 LDO（DLDO）。所提出的 DLDO 主要通过同步时钟信号的数字代码进行调节，同时根据负载电流水平动态调整栅极驱动电平。所提出的栅极调制方案可显著拓宽负载电流的动态范围，并降低输出电压纹波。此外，在自适应栅极调制的基础上还增加了一个异步电压下垂检测电路，以改善电压下垂并确保从负载瞬态中快速恢复。所提出的 DLDO 采用 28 纳米 CMOS 工艺制造。实现了 57 $143/times $ (1.4- $80~\mu $ A) 的动态负载范围，并在整个负载电流范围内测得低于 17 mV 的输出电压纹波。在各种负载瞬态条件下测得的响应时间小于 10 ns，恢复时间小于 30 ns。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Solid-State Circuits Letters Engineering-Electrical and Electronic Engineering

CiteScore

4.30

自引率

3.70%

发文量