IEEE Solid-State Circuits Letters最新文献_第8页

A 1.48-fs FoM Analog Capacitorless-LDO With Cascade-Inverter-Based Pseudo-Power Transistor 基于级联逆变器的1.48 fm模拟无电容ldo

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2024-12-25 DOI: 10.1109/LSSC.2024.3522785

Hing Tai Chen;Xun Liu;Ka Nang Leung

引用次数: 0

A 28-nm Static-Power-Free Fully Parallel RRAM-Based TD CIM Macro With 1982 TOPS/W/Bit for Edge Applications 用于边缘应用的28nm无静电全并行rram TD CIM微型机，具有1982 TOPS/W/Bit

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2024-12-19 DOI: 10.1109/LSSC.2024.3520593

Songtao Wei;Peng Yao;Xinying Guo;Dong Wu;Lu Jie;Qi Qin;Bin Gao;Jianshi Tang;He Qian;Sining Pan;Huaqiang Wu

引用次数: 0

Ultrasensitive Reset-Less Integrator-Based PIN-Diode Receiver With Input Current Control 基于输入电流控制的超灵敏无复位积分器PIN-Diode接收器

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2024-12-19 DOI: 10.1109/LSSC.2024.3520338

Christoph Gasser;Christoph Ribisch;Simon Michael Laube;Kerstin Schneider-Hornstein;Horst Zimmermann

引用次数: 0

Enhancing AI Acceleration: A Calibration-Free, PVT-Robust Analog Compute-in-Memory Macro With Activation Functions 增强AI加速：具有激活函数的免校准，pvt鲁棒模拟内存中计算宏

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2024-12-04 DOI: 10.1109/LSSC.2024.3510679

Hechen Wang;Renzhi Liu;Richard Dorrance;Deepak Dasalukunte;Niranjan Mylarappa Gowda;Brent Carlton

引用次数: 0

A 10-Gb/s Optical Receiver With Monolithically Integrated PIN Photodiode, Novel AGC, and Sensitivity of –27.1 dBm for BER 10-3 基于单片集成PIN光电二极管的10gb /s光接收机，新型AGC，误码率为-27.1 dBm

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2024-12-04 DOI: 10.1109/LSSC.2024.3511582

Wenyu Zhou;Larry Tarof;Rony E. Amaya

{"title":"A 10-Gb/s Optical Receiver With Monolithically Integrated PIN Photodiode, Novel AGC, and Sensitivity of –27.1 dBm for BER 10-3","authors":"Wenyu Zhou;Larry Tarof;Rony E. Amaya","doi":"10.1109/LSSC.2024.3511582","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3511582","url":null,"abstract":"A monolithically integrated optical receiver in InP for 10-Gb/s intensity modulation direct detect (IMDD) application is presented. The sensitivity at the bit error rate (BER) \u0000<inline-formula> <tex-math>$rm 10^{-3}$ </tex-math></inline-formula>\u0000 is measured to be –27.1 dBm. An integrated PIN diode photodetector (PD) minimizes the parasitics caused by wire bonds between the PD and the transimpedance amplifier (TIA). For the first time, electronics and photonics are monolithically integrated into a single InP IC. The avalanche photodetector (APD) is replaced with PIN PD, exhibiting comparable sensitivity and requiring a simple 3.3-V supply voltage. A single transistor voltage-to-current convertor between two cascaded TIAs performs automatic gain control (AGC). A total dynamic gain control of 9 dB has been demonstrated with a dynamic range of more than 17 dB, employing only four transistors and dissipating 8.5 mW. Improved gain peaking extends the operating bandwidth and makes it suitable for higher-speed applications. The power supply rejection ratio (PSRR) exceeds 24 dB without needing on-chip bandgap references.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"13-16"},"PeriodicalIF":2.2,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10778277","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142858878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 15.4-ppm/°C GaN-Based Voltage Reference With Process-Variation-Immunity and High PSR for Electric Vehicle Power Systems 一种15.4 ppm/°C、过程抗扰度和高PSR的基于gan的电动汽车电源基准电压

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2024-12-02 DOI: 10.1109/LSSC.2024.3510597

Po-Jui Chiu;Chi-Yu Chen;Xiao-Quan Wu;Yu-Ting Huang;Tz-Wun Wang;Sheng-Hsi Hung;Ke-Horng Chen;Kuo-Lin Zheng;Chih-Chen Li

引用次数: 0

An 828-μW 100.9-dB SNDR 20-kHz BW Zoom-Linear-Exponential Incremental ADC With Split Positive Feedback and Duty-Cycle Amplifier 一种828 μ w、100.9 db SNDR、20 khz BW、分路正反馈和占空比放大器的变焦线性指数增量ADC

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2024-12-02 DOI: 10.1109/LSSC.2024.3510423

Lairong Fang;Shuwen Zhang;Xiaoyang Zeng;Zhiliang Hong;Jiawei Xu

{"title":"An 828-μW 100.9-dB SNDR 20-kHz BW Zoom-Linear-Exponential Incremental ADC With Split Positive Feedback and Duty-Cycle Amplifier","authors":"Lairong Fang;Shuwen Zhang;Xiaoyang Zeng;Zhiliang Hong;Jiawei Xu","doi":"10.1109/LSSC.2024.3510423","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3510423","url":null,"abstract":"This letter presents a hybrid, three-step zoom-linear-exponential incremental analog-to-digital converter (ZLE-IADC) for audio applications. The zoom-SAR in the first step provides coarse signal quantization and relaxes the accuracy requirements of subsequent conversions. The second step utilizes a single-loop, first-order delta–sigma modulator (\u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000M). In the third step, the \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000M is reconfigured as an exponential counting loop with split positive feedback (SPF). The SPF isolates the loop integrator from the residue sampling network, thereby improving the settling time of the residue amplifier (RA) under the transient switching of linear-exponential loads. Besides, a duty-cycle RA further reduces its average power from 48.4% to 6.1% of the IADC. Last, the zoom-SAR in the first step is reconfigured as a gain-embedded quantizer (GEQ) in the third step, optimizing the hardware cost. Fabricated in a standard 180-nm CMOS technology, the proposed IADC achieves a dynamic range (DR) of 103.9 dB and a signal-to-noise-and-distortion ratio (SNDR) of 100.9 dB, which corresponds to a state-of-the-art Schreier \u0000<inline-formula> <tex-math>${mathrm { FoM}}_{mathrm { S,{mathrm {DR}}}}$ </tex-math></inline-formula>\u0000 of 177.7 dB.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"1-4"},"PeriodicalIF":2.2,"publicationDate":"2024-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142858876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 0.41-ns CLK-OUT Delay, 0.22-μVrms Input-Referred Noise CMOS Integration Dynamic Comparator With Flipping Capacitor for Charge Reuse 0.41-ns CLK-OUT 延迟、0.22-μVrms 输入延迟噪声 CMOS 集成动态比较器，带翻转电容器，可重复使用电荷

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2024-12-02 DOI: 10.1109/LSSC.2024.3510389

Kwok Cheong Li;Xinhang Xu;Jihang Gao;Siyuan Ye;Jiajia Cui;Yacong Zhang;Ru Huang;Linxiao Shen

引用次数: 0

A Reconfigurable, Multichannel Quantized-Analog Transmitter With <-35 dB EVM and <-51 dBc ACLR in 22-nm FDSOI 22纳米FDSOI中EVM <-35 dB、ACLR <-51 dBc的可重构多通道量化模拟发射机

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2024-11-29 DOI: 10.1109/LSSC.2024.3509378

John Zhong;Konstantinos Vasilakopoulos;Antonio Liscidini

引用次数: 0

A Two-Story Quad-Core Dual-Mode VCO in 65-nm CMOS 65纳米CMOS的两层四核双模VCO

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2024-11-27 DOI: 10.1109/LSSC.2024.3506672

Pingda Guan;Haikun Jia;Wei Deng;Ruichang Ma;Huabing Liao;Teerachot Siriburanon;Robert Bogdan Staszewski;Zhihua Wang;Baoyong Chi

{"title":"A Two-Story Quad-Core Dual-Mode VCO in 65-nm CMOS","authors":"Pingda Guan;Haikun Jia;Wei Deng;Ruichang Ma;Huabing Liao;Teerachot Siriburanon;Robert Bogdan Staszewski;Zhihua Wang;Baoyong Chi","doi":"10.1109/LSSC.2024.3506672","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3506672","url":null,"abstract":"To simultaneously advance phase noise (PN) performance at a wide frequency-tuning range (FTR) while using the standard supply levels, this letter proposes a multistory multicore multimode oscillator topology based on the following ideas: 1) the N number of cores reduces the PN by \u0000<inline-formula> <tex-math>$10 log (N)$ </tex-math></inline-formula>\u0000 dB, and the circular geometry of inductors promotes their high-quality \u0000<inline-formula> <tex-math>$(Q)$ </tex-math></inline-formula>\u0000-factors and compact layout; 2) the multiple stacked cores exploiting current reuse improve the figure of merit (FoM) using an nMOS-only oscillator configuration under a standard supply; and 3) the multiple modes expand the FTR by leveraging the interstory coupling with all oscillator cores turned on simultaneously, only occupying a single resonator’s footprint. A two-story quad-core dual-mode voltage-controlled oscillator (VCO) prototype is fabricated in 65-nm CMOS. Using a standard 1.2-V supply, it achieves PN of −111.3 to −106.2 dBc/Hz at 1-MHz offset over a 25.0–35.9-GHz FTR (35.8%), a 186.5–189.1-dBc/Hz FoM, and a 197.6–200.2-dBc/Hz \u0000<inline-formula> <tex-math>$rm {FoM}_{T}$ </tex-math></inline-formula>\u0000 (i.e., FoM with normalized FTR).","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"363-366"},"PeriodicalIF":2.2,"publicationDate":"2024-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142810333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0