IEEE Solid-State Circuits Letters最新文献_第8页

A Bootstrapped 250-nm GaN MMIC N-Path Filter With a 31 dBm In-Band P1dB 带内 P1dB 为 31 dBm 的自举式 250-nm GaN MMIC N-Path 滤波器

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-01-24 DOI: 10.1109/LSSC.2024.3358083

Netanel Desta;Emanuel Cohen

引用次数: 0

Compact Multifunctional 180° Hybrid-Based 300-GHz Subharmonic I/Q Downconversion Resistive Mixers in 130-nm SiGe Process 基于 180° 混合技术的紧凑型多功能 300-GHz 次谐波 I/Q 下变频电阻混频器，采用 130 纳米硅锗工艺制造

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-01-24 DOI: 10.1109/LSSC.2024.3357810

Liang Zhang;Fengjun Chen;Xu Cheng;Jiang-An Han;Xianhu Luo;Changxing Lin;Wei Su

{"title":"Compact Multifunctional 180° Hybrid-Based 300-GHz Subharmonic I/Q Downconversion Resistive Mixers in 130-nm SiGe Process","authors":"Liang Zhang;Fengjun Chen;Xu Cheng;Jiang-An Han;Xianhu Luo;Changxing Lin;Wei Su","doi":"10.1109/LSSC.2024.3357810","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3357810","url":null,"abstract":"In this letter, a compact multifunctional 180° hybrid suitable for subharmonic in-phase/quadrature (I/Q) mixers is proposed. To feed LO and RF signals at different frequencies and distribute dc supply, the hybrid combines an out-of-phase dual balun, two in-phase power dividers based on T-junction and coupled lines, and four zero-ohm transmission lines (ZTLs) into a single passive component. Chip size, insertion loss, and bandwidth can all be improved by reducing the number of passive components cascaded in the circuit. The proposed hybrid’s footprint is further minimized by employing redundant line and compensation capacitor techniques. In a 130-nm SiGe BiCMOS technology, two proof-of-concept subharmonic I/Q downconversion resistive mixers with/without an on-chip LO quadrupler are implemented. Both mixers feature wideband HBT-based IF amplifiers and emitter followers, which eliminate the need for dc-blocking capacitors that constrict the IF bandwidth. The mixer, without an integrated LO multiplier, occupies an area of \u0000<inline-formula> <tex-math>$0.685times 0.692,,{mathrm{ mm}}^{2}$ </tex-math></inline-formula>\u0000 and achieves a measured conversion gain of approximately 0 dB from 255 to 310 GHz. The mixer with an on-chip LO quadrupler exhibits a conversion gain of approximately −1 dB from 270 to 300 GHz and a 3-dB IF bandwidth from 0.01 to 7 GHz. Additionally, the measured image rejection ratio (IRR) is greater than 20 dB within the operating frequencies.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"86-89"},"PeriodicalIF":2.7,"publicationDate":"2024-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139942713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 28-GHz Low-Power Variable-Gain Low-Noise Amplifier Using Twice Current Reuse Technique 使用两倍电流重复使用技术的 28 千兆赫低功耗可变增益低噪声放大器

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-01-15 DOI: 10.1109/LSSC.2024.3354037

Yu-Teng Chang;Wen-Jie Lin

{"title":"A 28-GHz Low-Power Variable-Gain Low-Noise Amplifier Using Twice Current Reuse Technique","authors":"Yu-Teng Chang;Wen-Jie Lin","doi":"10.1109/LSSC.2024.3354037","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3354037","url":null,"abstract":"In this letter, a 28-GHz low-power variable-gain low-noise amplifier (VGLNA) is designed for fifth-generation millimeter-wave applications and implemented using the twice current reuse (CR) technique and a tunable load. This amplifier employing the twice CR technique exhibits low dc power while delivering enhanced gain. The gain control (GC) range of the amplifier is extended using a tunable load, which is composed of a pMOS device and an inductance, and the phase variation is improved by resonating the inductance with the parasitic capacitance of the intrastage CR amplifier. Because the tunable load selectively attenuates only ac signals, \u0000<inline-formula> <tex-math>${mathrm{ IP}}_{1 rm dB}$ </tex-math></inline-formula>\u0000 can be proportionally increased by reducing the gain. At 28 GHz, the measured gain and GC range are 21.2 and 13.8 dB, respectively. In the entire GC range, the measured \u0000<inline-formula> <tex-math>${mathrm{ IP}}_{1 rm dB}$ </tex-math></inline-formula>\u0000 ranges from −20 to −7 dBm, the noise figure (NF) ranges from 3.7 to 6.8 dB, and the RMS phase error is 1.05° at 28 GHz. At a supply voltage of 1.2 V, the dc power of the proposed VGLNA is only 5.0 mW. These results highlight that the proposed VGLNA has the lowest dc power, higher gain, and better figure of merit compared to other works.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"58-61"},"PeriodicalIF":2.7,"publicationDate":"2024-01-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139654811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Photovoltaic Energy Harvester/Image Sensor Platform With Event Detection Capability in 180 nm 具有事件检测能力的 180 纳米光伏能量收集器/图像传感器平台

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-01-12 DOI: 10.1109/LSSC.2024.3353381

D. Zagouri;A. Rimer;E. Emanovic;Y. Ninio;Y. Slezak;D. Jurisic;A. Fish;J. Shor

引用次数: 0

A Fully Synthesizable Fractional-N MDLL With Energy-Efficient Ring-Oscillator-Based DTC of Large Tuning Range 基于高能效环形振荡器的大调谐范围 DTC 的完全可合成分数 N MDLL

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-01-11 DOI: 10.1109/LSSC.2024.3352736

Hóngyè Huáng;Bangan Liu;Zezheng Liu;Dingxin Xu;Yuncheng Zhang;Waleed Madany;Junjun Qiu;Zheng Sun;Ashbir Aviat Fadila;Jian Pang;Zheng Li;Dongwon You;Atsushi Shirane;Kenichi Okada

{"title":"A Fully Synthesizable Fractional-N MDLL With Energy-Efficient Ring-Oscillator-Based DTC of Large Tuning Range","authors":"Hóngyè Huáng;Bangan Liu;Zezheng Liu;Dingxin Xu;Yuncheng Zhang;Waleed Madany;Junjun Qiu;Zheng Sun;Ashbir Aviat Fadila;Jian Pang;Zheng Li;Dongwon You;Atsushi Shirane;Kenichi Okada","doi":"10.1109/LSSC.2024.3352736","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3352736","url":null,"abstract":"This letter describes a fully synthesizable fractional-\u0000<inline-formula> <tex-math>$N$ </tex-math></inline-formula>\u0000 multiplexing delay-locked loop (MDLL) with a ring-oscillator-based digital-to-time converter (RO-DTC). The proposed RO-DTC can generate a wide range of time delays with only a relatively smaller number of delay cells. Since its structure is periodical, the corresponding predistortion look-up table (LUT)’s size could also be reduced. The proposed MDLL is implemented in a 65-nm CMOS process. The measured results show that the RO-DTC’s power normalized by operating frequency and tuning range is the lowest among other state-of-the-art works. The proposed MDLL achieves FoMs of −242.3 and −218.6 dB in integer-\u0000<inline-formula> <tex-math>$N$ </tex-math></inline-formula>\u0000 and fractional-\u0000<inline-formula> <tex-math>$N$ </tex-math></inline-formula>\u0000 operation modes at RF frequencies 1.04 and 1.0465 GHz. The core area is 0.0892 mm2.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"54-57"},"PeriodicalIF":2.7,"publicationDate":"2024-01-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10391060","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139654425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Mixer-First Receiver With On-Demand Passive Harmonic Rejection 具有按需无源谐波抑制功能的混频器优先接收器

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-01-09 DOI: 10.1109/LSSC.2024.3351671

Hongyu Lu;Hossein Rahmanian Kooshkaki;Patrick P. Mercier

引用次数: 0

A 85-Gb/s PAM-4 TIA With 2.2-mApp Maximum Linear Input Current in 28-nm CMOS 采用 28-nm CMOS、最大线性输入电流为 2.2 mApp 的 85 Gb/s PAM-4 TIA

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-01-09 DOI: 10.1109/LSSC.2024.3351683

Shuaizhe Ma;Zhenyu Yin;Nianquan Ran;Yifei Xia;Ruixuan Yang;Chuanhao Yu;Songqin Xu;Binhao Wang;Nan Qi;Bing Zhang;Jingbo Shi;Xiaoyan Gui;Li Geng;Dan Li

引用次数: 0

A Fully Integrated, Automatically Generated DC–DC Converter Maintaining >75% Efficiency From 398 K Down to 23 K Across Wide Load Ranges in 12-nm FinFET 全集成、自动生成的 DC-DC 转换器，在 12 纳米 FinFET 的宽负载范围内，从 398 K 降至 23 K，保持 >75% 的效率

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-01-01 DOI: 10.1109/LSSC.2023.3349129

Anhang Li;Jeongsup Lee;Prashansa Mukim;Brian D. Hoskins;Pragya Shrestha;David Wentzloff;David Blaauw;Dennis Sylvester;Mehdi Saligane

引用次数: 0

A 25-Gb/s 3-D Direct Bond Silicon Photonic Receiver in 12-nm FinFET 采用 12 纳米 FinFET 的 25-Gb/s 3-D 直接结合硅光子接收器

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2023-12-20 DOI: 10.1109/LSSC.2023.3345252

Peng Yan;Po-Hsuan Chang;Anirban Samanta;Mingye Fu;Yu Zhang;Mehmet Berkay On;Ankur Kumar;Hyungryul Kang;Il-Min Yi;Dedeepya Annabattuni;David Scott;Robert Patti;Yang-Hang Fan;Yuanming Zhu;S. J. Ben Yoo;Samuel Palermo

{"title":"A 25-Gb/s 3-D Direct Bond Silicon Photonic Receiver in 12-nm FinFET","authors":"Peng Yan;Po-Hsuan Chang;Anirban Samanta;Mingye Fu;Yu Zhang;Mehmet Berkay On;Ankur Kumar;Hyungryul Kang;Il-Min Yi;Dedeepya Annabattuni;David Scott;Robert Patti;Yang-Hang Fan;Yuanming Zhu;S. J. Ben Yoo;Samuel Palermo","doi":"10.1109/LSSC.2023.3345252","DOIUrl":"https://doi.org/10.1109/LSSC.2023.3345252","url":null,"abstract":"This letter presents a 25-Gb/s 3D-integrated optical receiver, which consists of an electronic integrated circuit (EIC) die fabricated in 12-nm FinFET technology and a photonic integrated circuit (PIC) die fabricated in AIM Photonics’ integrated photonic technology. EIC is flip-chip bonded to PIC through direct bond interconnect (DBI), allowing for significantly reduced parasitic. Except for reduced input-referred noise thanks to improvements in PIC and packaging, variable bandwidth transimpedance amplifier (TIA) with multistage feedback amplifier is utilized for further noise reduction and front-end bandwidth compensation for better full-link energy efficiency. This TIA is followed by a broadband amplifier with active inductor loading, dc cancellation loop, RC LPF generating the pseudo-differential signal, 4 quarter-rate slicers, and a 4-to-8 de-serializer. Measurements demonstrate −17.0-dBm optical modulation amplitude (OMA) sensitivity at 25 Gb/s with 2.12-mW receiver power and 2.66-mW receiver clocking power, which translates to 191.2 and 84.8 fJ/bit receiver energy efficiency, with and without per-channel injection-locked oscillator (ILO) power. Each receiver channel occupies \u0000<inline-formula> <tex-math>$1560 mu {}text{m} ^{mathrm{ 2}}$ </tex-math></inline-formula>\u0000. To the author’s best knowledge, it is the best OMA sensitivity, energy efficiency, and silicon area simultaneously achieved among published 25 Gb/s optical receivers.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"34-37"},"PeriodicalIF":2.7,"publicationDate":"2023-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139488218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Ultralow-Power H.264/AVC Intra-Frame Image Compression Accelerator for Intelligent Event-Driven IoT Imaging Systems 用于智能事件驱动物联网成像系统的超低功耗 H.264/AVC 帧内图像压缩加速器

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2023-12-20 DOI: 10.1109/LSSC.2023.3344699

Qirui Zhang;Hyochan An;Andrea Bejarano-Carbo;Hun-Seok Kim;David Blaauw;Dennis Sylvester

{"title":"An Ultralow-Power H.264/AVC Intra-Frame Image Compression Accelerator for Intelligent Event-Driven IoT Imaging Systems","authors":"Qirui Zhang;Hyochan An;Andrea Bejarano-Carbo;Hun-Seok Kim;David Blaauw;Dennis Sylvester","doi":"10.1109/LSSC.2023.3344699","DOIUrl":"https://doi.org/10.1109/LSSC.2023.3344699","url":null,"abstract":"This letter presents an ultralow-power (ULP) H.264/AVC intra-frame image compression accelerator tailored for intelligent event-driven ULP IoT imaging systems. The H.264/AVC intra-frame codec is customized to enable compression of arbitrary nonrectangular change-detected regions. To optimize energy and latency from image memory accesses, novel algorithm-hardware co-designs are proposed for intra-frame predictions, reducing overhead for neighbor macroblock (McB) accesses by \u0000<inline-formula> <tex-math>$2.6times $ </tex-math></inline-formula>\u0000 at a negligible quality loss. With split control for major processing phases, latency is optimized by exploiting data dependency and pipelining. Area and leakage of major computation units are reduced through data path micro-architecture reconfiguration. Fabricated in 40 nm, it occupies a mere 0.32 mm2 area with 4-kB SRAM. At 0.6 V and 153 kHz, it consumes only \u0000<inline-formula> <tex-math>$1.21 {mu }text{W}$ </tex-math></inline-formula>\u0000, with 30.9 pJ/pixel compression energy efficiency that rivals state-of-the-art designs. For an event-driven IoT imaging system, the combination of the proposed accelerator and change detection brings \u0000<inline-formula> <tex-math>$133times $ </tex-math></inline-formula>\u0000 reduction to the overall energy for regressing an image of change-detected region of interest.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"30-33"},"PeriodicalIF":2.7,"publicationDate":"2023-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139488220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0