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IEEE Solid-State Circuits Letters最新文献

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A Ka-Band Mutual Coupling Resilient Stacked-FET Power Amplifier With 21.2 dBm OP1dB and 27.6% PAE1dB in 45-nm CMOS SOI 45 纳米 CMOS SOI 中具有 21.2 dBm OP1dB 和 27.6% PAE1dB 的 Ka 波段抗互耦叠加场效应晶体管功率放大器
IF 2.7
IEEE Solid-State Circuits Letters Pub Date : 2024-04-10 DOI: 10.1109/LSSC.2024.3386676
Jian Zhang;Dawei Wang;Wei Zhu;Ming Zhai;Xiangjie Yi;Yan Wang
{"title":"A Ka-Band Mutual Coupling Resilient Stacked-FET Power Amplifier With 21.2 dBm OP1dB and 27.6% PAE1dB in 45-nm CMOS SOI","authors":"Jian Zhang;Dawei Wang;Wei Zhu;Ming Zhai;Xiangjie Yi;Yan Wang","doi":"10.1109/LSSC.2024.3386676","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3386676","url":null,"abstract":"This letter presents a Ka-band mutual coupling resilient stacked-FET power amplifier (PA) in 45-nm CMOS silicon on insulator. Two sub-PAs with triple-stacked-FET to increase output-power (Pout) are combined through a quadrature hybrid coupler to keep robust and high performance in the scenario of mutual coupling among the phased-array antennas. A shunt inductor is introduced to deal with the performance deterioration caused by the transistors’ parasitic capacitances and the magnetic coupling cancelling topology is adopted for a more compact layout. The measurement results show that the proposed PA achieves 21.2 dBm OP1dB with 27.6% PAE1dB and 22.2 dBm Psat with 28.8% peak PAE. The OP1dB and PAE1dB are beyond 21 dBm and 22% for a frequency range from 25 to 32 GHz, respectively. The maximum small-signal gain is 26.5 dB with <-19/-14 dB S11/S22. The simulated variation of Psat/OP1dB is less than 0.5/1.1 dBm under a strong voltage-standing-wave-ratio condition.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"147-150"},"PeriodicalIF":2.7,"publicationDate":"2024-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140647929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
248-GHz Subharmonic Mixer Last Transmitter With I/Q Imbalance and LO Feedthrough Calibration 具有 I/Q 不平衡和 LO 馈入校准功能的 248-GHz 次谐波混频器末级发射机
IF 2.7
IEEE Solid-State Circuits Letters Pub Date : 2024-04-10 DOI: 10.1109/LSSC.2024.3387285
Seunghoon Lee;Junhyeong Kim;Kangseop Lee;Ho-Jin Song
{"title":"248-GHz Subharmonic Mixer Last Transmitter With I/Q Imbalance and LO Feedthrough Calibration","authors":"Seunghoon Lee;Junhyeong Kim;Kangseop Lee;Ho-Jin Song","doi":"10.1109/LSSC.2024.3387285","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3387285","url":null,"abstract":"This letter presents a 248 GHz compact direct-conversion transmitter with IQ and LO feedthrough (LOFT) calibration capability, which can achieve a data rate of 20-Gb/s with 16-QAM. The transmitter design incorporates a subharmonic double-balanced mixer configuration, simplifying the complexity of the local oscillator (LO) chain. Furthermore, a Wilkinson power divider and a transmission line terminated by variable capacitors are used to generate LO signals with a 45° phase difference. This configuration, combined with variable gain amplifiers, allows for the precise balancing of IQ amplitude and phase. The measured image rejection ratio and LOFT suppression ratio are better than 25 and 28 dB, respectively, in the range of 242–252 GHz. The DC power consumption of the transmitter is 96.3 mW.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"159-162"},"PeriodicalIF":2.7,"publicationDate":"2024-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140818799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Fully Integrated Digital LDO With Adaptive Sampling and Statistical Comparator Selection 具有自适应采样和统计比较器选择功能的全集成数字 LDO
IF 2.7
IEEE Solid-State Circuits Letters Pub Date : 2024-04-04 DOI: 10.1109/LSSC.2024.3385233
Shun Yamaguchi;Takashi Hisakado;Osami Wada;Mahfuzul Islam
{"title":"A Fully Integrated Digital LDO With Adaptive Sampling and Statistical Comparator Selection","authors":"Shun Yamaguchi;Takashi Hisakado;Osami Wada;Mahfuzul Islam","doi":"10.1109/LSSC.2024.3385233","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3385233","url":null,"abstract":"Digital LDOs are gaining attention for their operation with small output capacitance. Adaptive sampling with a large frequency scaling ratio is required for fast transient response with low-power operation. Furthermore, the design of a fluctuation detector to deal with large load steps is important. This letter describes an adaptive-sampling digital LDO with a built-in clock generator and fluctuation detector based on statistical comparator selection. Statistical comparator selection utilizes offset voltage variation to realize stable implicit references. We apply order statistics for run-time calibration. Our proposed LDO fabricated in a commercial 65-nm low-power CMOS process operates from 0.6 to 1.2 V and achieves a maximum current efficiency of 99.99 %. The transient FoM is 0.25 ps.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"163-166"},"PeriodicalIF":2.7,"publicationDate":"2024-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140818784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Subthreshold Time-Domain Analog Spiking Neuron With PLL-Based Leak Circuit and Capacitive DAC Synapse 基于 PLL 泄漏电路和电容式 DAC 突触的阈下时域模拟尖峰神经元
IF 2.7
IEEE Solid-State Circuits Letters Pub Date : 2024-04-04 DOI: 10.1109/LSSC.2024.3384762
Taylor Barton;Shea Smith;Yu Hao;Ryan Watson;Kyle Rogers;Parker Allred;Bibhu Datta Sahoo;Nancy Fulda;Jordan T. Yorgason;Karl F. Warnick;Mau-Chung Frank Chang;Yen-Cheng Kuan;Shiuh-Hua Wood Chiang
{"title":"A Subthreshold Time-Domain Analog Spiking Neuron With PLL-Based Leak Circuit and Capacitive DAC Synapse","authors":"Taylor Barton;Shea Smith;Yu Hao;Ryan Watson;Kyle Rogers;Parker Allred;Bibhu Datta Sahoo;Nancy Fulda;Jordan T. Yorgason;Karl F. Warnick;Mau-Chung Frank Chang;Yen-Cheng Kuan;Shiuh-Hua Wood Chiang","doi":"10.1109/LSSC.2024.3384762","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3384762","url":null,"abstract":"The design and measurement of a time-domain analog spiking neuron is described. The proposed neuron leverages time-domain processing using voltage-controlled oscillators (VCOs) and a time-domain comparator to integrate the input spike and trigger the output spike. A novel leaky circuit uses a phase-locked loop (PLL) to drive the phase difference between the two VCOs toward zero. A weighted capacitive digital-to-analog converter (CDAC) synapse merges the input spikes and phase-frequency detector (PFD) outputs to generate the VCO control voltage. The neuron is implemented in a 28-nm CMOS technology and operates under a subthreshold supply voltage of 0.35 V. Occupying \u0000<inline-formula> <tex-math>$154~mu {mathrm{ m}}^{2}$ </tex-math></inline-formula>\u0000, measurement shows a maximum spike rate of 5.5 MHz and energy consumption of 159 fJ/spike.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"143-146"},"PeriodicalIF":2.7,"publicationDate":"2024-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140639424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and Stability Analysis of the Variable-Sawtooth-Based PWM Controller for the AC-Coupled Envelope Tracking Supply Modulator 用于交流耦合包络跟踪电源调制器的基于可变锯齿的 PWM 控制器的设计和稳定性分析
IF 2.7
IEEE Solid-State Circuits Letters Pub Date : 2024-04-02 DOI: 10.1109/LSSC.2024.3384345
Peng Xu;Tao Wang;Xueli Zhang;Peng Cao;Jiawei Xu;Zhiliang Hong
{"title":"Design and Stability Analysis of the Variable-Sawtooth-Based PWM Controller for the AC-Coupled Envelope Tracking Supply Modulator","authors":"Peng Xu;Tao Wang;Xueli Zhang;Peng Cao;Jiawei Xu;Zhiliang Hong","doi":"10.1109/LSSC.2024.3384345","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3384345","url":null,"abstract":"This letter analyzes the proposed variable-sawtooth-based PWM controller for the ac-coupled envelope tracking (ET) supply modulator (SM). The ET SM includes a linear amplifier and a switching power modulator (SPM). The SPM maintains the voltage across the ac-coupling capacitor and provides an output current in a power-efficient manner. A 10-MHz constant frequency is employed in the proposed SPM to reduce the interference to the communication system. It utilizes a pulse-width-modulation controller but contains a voltage main loop and a current auxiliary loop, improving the transient response performance at the expense of complicated control loops. This letter analyzes the stability condition and design methodology to determine key parameters. The simulation and measurement have verified these theoretical analyses.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"151-154"},"PeriodicalIF":2.7,"publicationDate":"2024-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140813914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An 18-nW CMOS Current and Voltage Reference Circuit With Low Line Sensitivity and Wide Temperature Range 具有低线路灵敏度和宽温度范围的 18-nW CMOS 电流和电压基准电路
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-03-30 DOI: 10.1109/LSSC.2024.3407583
I-Fan Lin;Yu-Chu Tsai;Heng-Li Lin;Yu-Te Liao
{"title":"An 18-nW CMOS Current and Voltage Reference Circuit With Low Line Sensitivity and Wide Temperature Range","authors":"I-Fan Lin;Yu-Chu Tsai;Heng-Li Lin;Yu-Te Liao","doi":"10.1109/LSSC.2024.3407583","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3407583","url":null,"abstract":"This letter presents a design for a voltage and current reference (VCR) that utilizes a 0.18-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m CMOS process. The design employs stacked-diode MOS transistors (SDMTs) to generate a voltage that is complementary to absolute temperature for the current reference (CR). By adjusting the transistor size ratio, this bias voltage exhibits the similar temperature coefficient (TC) as that of the resistor in the CR. To enhance temperature compensation, a reversely biased transistor is employed in the voltage reference (VR). Additionally, the cascode current mirror and SDMTs in the VR mitigate supply sensitivity in both voltage and current outputs. The VCR achieves a TC of 124 ppm/°C in VR and 264 ppm/°C in CR over a temperature range of \u0000<inline-formula> <tex-math>$- 40~^{circ }$ </tex-math></inline-formula>\u0000C to \u0000<inline-formula> <tex-math>$130~^{circ }$ </tex-math></inline-formula>\u0000C. Furthermore, it achieves a line sensitivity of 0.011 %/V in VR and 0.094 %/V in CR while operating at 18.51 nW at room temperature. The active chip area of the VCR is approximately \u0000<inline-formula> <tex-math>$25~000~mu $ </tex-math></inline-formula>\u0000m2.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"179-182"},"PeriodicalIF":2.2,"publicationDate":"2024-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141474867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 23.9-μW 13.6-Bit Period Modulation-Based Capacitance-to-Digital Converter With Dynamic Current Mirror Front-End 带动态电流镜前端的 23.9μW 13.6 位基于周期调制的电容数字转换器
IF 2.7
IEEE Solid-State Circuits Letters Pub Date : 2024-03-28 DOI: 10.1109/LSSC.2024.3382813
Hyeyeon Lee;Donguk Seo;Young-Jin Woo;Yoonmyung Lee;Inhee Lee;Youngcheol Chae
{"title":"A 23.9-μW 13.6-Bit Period Modulation-Based Capacitance-to-Digital Converter With Dynamic Current Mirror Front-End","authors":"Hyeyeon Lee;Donguk Seo;Young-Jin Woo;Yoonmyung Lee;Inhee Lee;Youngcheol Chae","doi":"10.1109/LSSC.2024.3382813","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3382813","url":null,"abstract":"This letter proposes a low-power high-precision capacitance-to-digital converter (CDC) utilizing a dynamic current mirror (DCM) to transform a sensor input capacitance \u0000<inline-formula> <tex-math>$(C_{mathrm{ IN}})$ </tex-math></inline-formula>\u0000 into an output current. The resulting current is directly proportional to the ratio of \u0000<inline-formula> <tex-math>$C_{mathrm{ IN}}$ </tex-math></inline-formula>\u0000 to an internal reference capacitor \u0000<inline-formula> <tex-math>$(C_{mathrm {REF}})$ </tex-math></inline-formula>\u0000 and subsequently converted into a period-modulated output, facilitating simple digitization by a digital counter. The CDC achieves an extensive \u0000<inline-formula> <tex-math>$C_{mathrm{ IN}}$ </tex-math></inline-formula>\u0000 range of 1 to 68 pF without the need for a power-hungry reference buffer. Fabricated in a 65-nm CMOS process, the prototype IC occupies a small area of 0.05-mm2 and consumes only \u0000<inline-formula> <tex-math>$23.9~mu text{W}$ </tex-math></inline-formula>\u0000 even with a \u0000<inline-formula> <tex-math>$C_{mathrm{ IN}}$ </tex-math></inline-formula>\u0000 of 47 pF. It achieves a capacitance resolution of 1.65 fF for a \u0000<inline-formula> <tex-math>$C_{mathrm{ IN}}$ </tex-math></inline-formula>\u0000 of 1 pF with a conversion time of 4 ms, corresponding to a 13.6-bit effective number of bit.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"135-138"},"PeriodicalIF":2.7,"publicationDate":"2024-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140606068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Compact Phase-Domain Delta–Sigma Time-to-Digital Converter With 8.5-ps Resolution for LiDAR Applications 用于激光雷达应用的 8.5 ps 分辨率紧凑型相位域三角积分时数字转换器
IF 2.7
IEEE Solid-State Circuits Letters Pub Date : 2024-03-27 DOI: 10.1109/LSSC.2024.3382594
Yoondeok Na;Myung-Jae Lee;Youngcheol Chae
{"title":"A Compact Phase-Domain Delta–Sigma Time-to-Digital Converter With 8.5-ps Resolution for LiDAR Applications","authors":"Yoondeok Na;Myung-Jae Lee;Youngcheol Chae","doi":"10.1109/LSSC.2024.3382594","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3382594","url":null,"abstract":"This letter introduces a compact, high-resolution time-to-digital converter (TDC) for lidar applications. In contrast to a conventional histogram-based peak detection method, this letter proposes a mean detection method using a highly digitized phase-domain delta–sigma (PD\u0000<inline-formula> <tex-math>$Delta Sigma$ </tex-math></inline-formula>\u0000) TDC. The proposed TDC operates in an incremental \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000 manner for a compact implementation and utilizing a digital integrator as a loop filter that facilitates an extended counting, resulting in significantly improved resolution. By utilizing a dual gated-ring oscillator (GRO) structure, time-quantization noise due to a residue phase of GRO is effectively mitigated. To address the issue of single-photon avalanche diode (SPAD) signals due to their stochastic nature, a dual time window is proposed to compensate for counting error when SPAD trigger missing occurs. Fabricated in a 65-nm CMOS process, the prototype TDC occupies only an area of \u0000<inline-formula> <tex-math>$2000~mu text{m}~^{mathrm{ 2}}$ </tex-math></inline-formula>\u0000. It achieves a noise level of 27.6 ps for the number of cycles of 32. When the cycle is 1000, it achieves a maximum integral nonlinearity (INL) of 80 ps (+53 ps/-27 ps) with a resolution of 8.5 ps.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"127-130"},"PeriodicalIF":2.7,"publicationDate":"2024-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140559311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 50–67-GHz Transformer-Based Six-Port Balanced-to-Unbalanced Quadrature Hybrid Coupler 基于变压器的 50-67-GHz 六端口平衡至不平衡正交混合耦合器
IF 2.7
IEEE Solid-State Circuits Letters Pub Date : 2024-03-26 DOI: 10.1109/LSSC.2024.3381811
Yang Gao;Howard C. Luong
{"title":"A 50–67-GHz Transformer-Based Six-Port Balanced-to-Unbalanced Quadrature Hybrid Coupler","authors":"Yang Gao;Howard C. Luong","doi":"10.1109/LSSC.2024.3381811","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3381811","url":null,"abstract":"This letter presents the first on-chip transformer-based six-port balanced-to-unbalanced quadrature hybrid coupler (QHBC). The proposed six-port QHBC employs three transformers to replace eight inductors design in conventional LC-based couplers for miniaturization. Fabricated in CMOS 28 nm, the overall size of the proposed coupler is 0.23 mm \u0000<inline-formula> <tex-math>$times0.17$ </tex-math></inline-formula>\u0000 mm, which is equivalent to \u0000<inline-formula> <tex-math>$0.046cdot lambda _{0} times 0.034cdot lambda _{0}$ </tex-math></inline-formula>\u0000, around 20 times smaller compared to the state-of-the-art six-port QHBC. Operating from 48 to 67 GHz, the measured differential and common mode return loss are <−8>−2.2 dB, respectively. The measured output phase and magnitude imbalance are within 10° and 2 dB, respectively. The measured voltage gain varies from −5.8 to −2.8 dB.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"139-142"},"PeriodicalIF":2.7,"publicationDate":"2024-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140619579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Corrections to “A Dynamic Power-Only Compute-in-Memory Macro With Power-of-Two Nonlinear SAR ADC for Nonvolatile Ferroelectric Capacitive Crossbar Array” 对 "用于非易失性铁电电容式交叉排列的动态只需电源的内存计算宏与两功率非线性 SAR ADC "的更正
IF 2.7
IEEE Solid-State Circuits Letters Pub Date : 2024-03-21 DOI: 10.1109/LSSC.2024.3371728
Injune Yeo;Wangxin He;Yuan-Chun Luo;Shimeng Yu;Jae-Sun Seo
{"title":"Corrections to “A Dynamic Power-Only Compute-in-Memory Macro With Power-of-Two Nonlinear SAR ADC for Nonvolatile Ferroelectric Capacitive Crossbar Array”","authors":"Injune Yeo;Wangxin He;Yuan-Chun Luo;Shimeng Yu;Jae-Sun Seo","doi":"10.1109/LSSC.2024.3371728","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3371728","url":null,"abstract":"In the article \u0000<xref>[1]</xref>\u0000, \u0000<xref>Table 2</xref>\u0000 was incorrectly copied from Table I. The correct \u0000<xref>Table 2</xref>\u0000 in \u0000<xref>[1]</xref>\u0000 is shown below.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"110-110"},"PeriodicalIF":2.7,"publicationDate":"2024-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10477667","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140188372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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