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IEEE Solid-State Circuits Letters最新文献

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A 37.8 Mb/mm² SRAM in Intel 18A Technology Featuring a Resistive Supply-Line Write Scheme and Write-Assist With Parallel Boost Injection 采用英特尔18A技术的37.8 Mb/mm²SRAM，具有电阻供电线路写入方案和并行升压注入的写入辅助
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-11-03 DOI: 10.1109/LSSC.2025.3628176
Harold Pilo;Manish Arora;Chien-An Lai;Mike Lee;Zack Lo;Mayur Randeria
{"title":"A 37.8 Mb/mm² SRAM in Intel 18A Technology Featuring a Resistive Supply-Line Write Scheme and Write-Assist With Parallel Boost Injection","authors":"Harold Pilo;Manish Arora;Chien-An Lai;Mike Lee;Zack Lo;Mayur Randeria","doi":"10.1109/LSSC.2025.3628176","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3628176","url":null,"abstract":"A high-density (HD), SRAM-based register file (RF) has been demonstrated in Intel 18A Technology (Wang et al., 2025 and Pilo et al., 2025) featuring RibbonFET GAA transistors and a back side power delivery network (BSDPN). The RF is optimized for HD and array efficiency and achieves a density of 37.8 Mb/mm2, the highest density reported to date for an RF in the most advanced technology nodes (Wang et al., 2025, Chang et al., 2025, and Pilo et al., 2025). It is implemented with a conventional bitline (BL), two-bank memory architecture and it can be used as the SRAM workhorse for most SoC applications with maximum bit-count of 262Kb.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"357-360"},"PeriodicalIF":2.0,"publicationDate":"2025-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145510085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.8-μm 32-Mpixel Always-On CMOS Image Sensor With Windmill-Pattern Edge Extraction and On-Chip DNN 基于风车模式边缘提取和片上深度神经网络的0.8 μm 32万像素CMOS图像传感器
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-11-03 DOI: 10.1109/LSSC.2025.3628314
Mamoru Sato;Sachio Akebono;Kazuyoshi Yasuoka;Eriko Kato;Masahiro Tsuruta;Chiaki Takano;Kensuke Ota;Kazuki Haraguchi;Masahiro Watanabe;Genki Fujii;Koichiro Yamanaka;Kazunori Yasuda;Satoshi Minami;Katsuhiko Hanzawa;Kohei Matsuda;Akihiko Kato;Yosuke Ueno
{"title":"A 0.8-μm 32-Mpixel Always-On CMOS Image Sensor With Windmill-Pattern Edge Extraction and On-Chip DNN","authors":"Mamoru Sato;Sachio Akebono;Kazuyoshi Yasuoka;Eriko Kato;Masahiro Tsuruta;Chiaki Takano;Kensuke Ota;Kazuki Haraguchi;Masahiro Watanabe;Genki Fujii;Koichiro Yamanaka;Kazunori Yasuda;Satoshi Minami;Katsuhiko Hanzawa;Kohei Matsuda;Akihiko Kato;Yosuke Ueno","doi":"10.1109/LSSC.2025.3628314","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3628314","url":null,"abstract":"This letter presents a CMOS image sensor (CIS) that integrates two operation modes: 1) a high-resolution viewing mode with <inline-formula> <tex-math>$0.8~mu $ </tex-math></inline-formula>m 32 Mpixels and 2) a low-power always-on object recognition mode consuming 2.67 mW at 10 frames/s. The CIS features a unique windmill-pattern analog edge extraction circuit that is resilient to illumination variations. An on-chip deep neural network processor was implemented alongside a compact algorithm with only 12 kB for coefficients and 48 kB for working memory. The design incorporates separate circuit areas for high-speed viewing and low-power sensing modes, thereby ensuring optimal performance and energy efficiency.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"353-356"},"PeriodicalIF":2.0,"publicationDate":"2025-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145510088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 560 μ W, 6 fA/√Hz, 146 dB-DR Ultrasensitive Current Readout Circuit for PWM-Dimming-Tolerant Under-Display Ambient Light Sensors 一种560 μ W、6 fA/√Hz、146 dB-DR的pwm耐调光显示环境光传感器超灵敏电流读出电路
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-10-30 DOI: 10.1109/LSSC.2025.3626378
Xiuzhi Zhao;Liheng Liu;Shi Chen;Tianxiang Qu;Qinjing Pan;Dan Li;Gan Guo;Zhiliang Hong;Jiawei Xu
{"title":"A 560 μ W, 6 fA/√Hz, 146 dB-DR Ultrasensitive Current Readout Circuit for PWM-Dimming-Tolerant Under-Display Ambient Light Sensors","authors":"Xiuzhi Zhao;Liheng Liu;Shi Chen;Tianxiang Qu;Qinjing Pan;Dan Li;Gan Guo;Zhiliang Hong;Jiawei Xu","doi":"10.1109/LSSC.2025.3626378","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3626378","url":null,"abstract":"This letter presents an ultralow-noise, power-efficient, and pulse-width modulation (PWM)-dimming-tolerant photocurrent readout circuit for under-display ambient light sensor (ALS). A transimpedance amplifier (TIA) with a feedback diode achieves G<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>-level resistance and 6 fA/<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>Hz input current noise, enabling sub-pA resolution. Instability and noise folding are mitigated at low power through a signal-dependent auto-tracking zero for frequency compensation and a low-pass filter for high-frequency noise suppression. A 2-point calibration algorithm improves the linearity of the current-to-frequency (I2F) quantizer without incurring additional power. To extract ambient light in the presence of PWM dimming interference, the readout supports under-sampling, allowing digital cancellation of interference. Fabricated in 180 nm CMOS, the prototype achieves <inline-formula> <tex-math>$0.36~rm pA_{pp}$ </tex-math></inline-formula> resolution, 146.3 dB dynamic range (DR), and a 206.3 dB <inline-formula> <tex-math>$rm FoM_{DR}$ </tex-math></inline-formula> in 0.84 ms readout time, representing best-in-class performance. Optical ALS measurements under PWM dimming interference are experimentally validated.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"361-364"},"PeriodicalIF":2.0,"publicationDate":"2025-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145510087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
PANNA: A 558 TOPS/W Pipelined All-Analog Neural Network Accelerator in 22 nm FD-SOI PANNA：一个558 TOPS/W流水线全模拟神经网络加速器在22纳米FD-SOI
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-10-30 DOI: 10.1109/LSSC.2025.3627274
Jakob Finkbeiner;Raphael Nägele;Manuel Wittlinger;Markus Grözing;Manfred Berroth;Georg Rademacher
{"title":"PANNA: A 558 TOPS/W Pipelined All-Analog Neural Network Accelerator in 22 nm FD-SOI","authors":"Jakob Finkbeiner;Raphael Nägele;Manuel Wittlinger;Markus Grözing;Manfred Berroth;Georg Rademacher","doi":"10.1109/LSSC.2025.3627274","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3627274","url":null,"abstract":"Analog computing offers intrinsic energy and latency benefits that makes it attractive for real-time and edge applications. Conventional analog accelerators suffer from repeated conversions between analog and digital domain, which degrades efficiency and throughput. We propose an all-analog pipelined neural network accelerator architecture in 22 nm fully-depleted silicon-on-insulator (FD-SOI) complementary metal-oxide-semiconductor (CMOS). Measurements of a demonstrator ASIC with analog I/Os and 6 bit weights are presented. The system energy efficiency is 290 TOPS/W or 558 TOPS/W if the energy for bias generation is neglected. The pipelined architecture achieves a throughput of 500M inferences/s and a latency of 1 ns/layer.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"365-368"},"PeriodicalIF":2.0,"publicationDate":"2025-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145510089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 200 GHz Wideband and Low-Power Direct-Downconversion Receiver Element in 16 nm FinFET Technology 一种用于16nm FinFET技术的200ghz宽带低功耗直接下变频接收器元件
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-10-28 DOI: 10.1109/LSSC.2025.3626442
Ethan Chou;Hesham Beshary;Nima Baniasadi;Ali M. Niknejad
{"title":"A 200 GHz Wideband and Low-Power Direct-Downconversion Receiver Element in 16 nm FinFET Technology","authors":"Ethan Chou;Hesham Beshary;Nima Baniasadi;Ali M. Niknejad","doi":"10.1109/LSSC.2025.3626442","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3626442","url":null,"abstract":"This letter presents a wideband and low-power direct-downconversion 200 GHz receiver element for digital-beamforming applications implemented in 16 nm FinFET technology. Wideband and low integrated receiver noise figure of 9.8 dB across a 21 GHz baseband bandwidth is realized with a differential low-noise amplifier leveraging an active input balun stage, while wideband gain of 29 dB with a 3-dB bandwidth at RF of 42 GHz is maintained throughout the receiver chain. Low-loss I/Q splitting and current-efficient variable-gain baseband amplification enable relatively low total DC power consumption of 130 mW, including the LO chain. The high instantaneous bandwidth and low power consumption enable potentially high data rates with high energy efficiency.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"349-352"},"PeriodicalIF":2.0,"publicationDate":"2025-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145510086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
3D-IC Chiplet Integrated Power Supply With LDO, SCVR, and Buck DC–DC Converter 带有LDO， SCVR和降压DC-DC转换器的3D-IC芯片集成电源
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-10-22 DOI: 10.1109/LSSC.2025.3624096
Xiaosen Liu;Xichen Sun;Renwei Chen;Haozhe Zhang;Zhoutong Liu;Yan Wang
{"title":"3D-IC Chiplet Integrated Power Supply With LDO, SCVR, and Buck DC–DC Converter","authors":"Xiaosen Liu;Xichen Sun;Renwei Chen;Haozhe Zhang;Zhoutong Liu;Yan Wang","doi":"10.1109/LSSC.2025.3624096","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3624096","url":null,"abstract":"With the rapid advancement of chiplet and heterogenous integration technologies, delivering power through the package, redistribution layer (RDL), and chip layers in 3-D space has become a fundamental challenge for high-performance SoCs. This letter provides a comprehensive overview of power delivery solutions, including low-dropout regulator (LDOs), switched capacitor converters, and Buck converters. It further details and compares advanced techniques such as novel conversion topologies, control schemes, optimization strategies, and integration strategies, offering insights into overcoming the power wall in emerging 3D-ICs.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"341-344"},"PeriodicalIF":2.0,"publicationDate":"2025-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145405387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An 8-Bit 400-MS/s 1-Then-2-Bit/Cycle SAR ADC With Comparator Rotation-Based Input-Independent Background Offset Calibration 基于比较器旋转的输入无关背景偏移校准的8位400毫秒/秒1- 2位/周期SAR ADC
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-10-22 DOI: 10.1109/LSSC.2025.3624263
Changjoo Kim;Sooho Park;Yohan Choi;Minkyun Shim;Woojin Lee;Donghwi Seo;Chulwoo Kim
{"title":"An 8-Bit 400-MS/s 1-Then-2-Bit/Cycle SAR ADC With Comparator Rotation-Based Input-Independent Background Offset Calibration","authors":"Changjoo Kim;Sooho Park;Yohan Choi;Minkyun Shim;Woojin Lee;Donghwi Seo;Chulwoo Kim","doi":"10.1109/LSSC.2025.3624263","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3624263","url":null,"abstract":"This letter presents an 8-bit 400 MS/s 1-then-2-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC) employing a comparator rotation-based background offset calibration (CRBC) technique. Unlike conventional 1-then-2-bit/cycle architectures, where calibration validity depends on the input voltage, the proposed comparator rotation-based background calibration enables input-independent background calibration, ensuring rapid calibration convergence and the reliable detection of time-varying errors, irrespective of input conditions. The prototype ADC was fabricated in 28 nm CMOS technology and achieves a signal-to-noise and distortion ratio (SNDR) of 42.9 dB and a spurious-free dynamic range (SFDR) of 56.5 dB at the Nyquist frequency. It consumes 1.67 mW at 400 MS/s, resulting in a Walden figure-of-merit (FoMW) of 36.6 fJ/conversion-step.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"345-348"},"PeriodicalIF":2.0,"publicationDate":"2025-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Wideband Calibration-Free D-Band Passive Phase Shifter With Frequency-Invariant Codes Over 24% Fractional Bandwidth 一种具有24%分数带宽的频率不变码的宽带无源移相器
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-10-15 DOI: 10.1109/LSSC.2025.3622233
Basem Abdelaziz Abdelmagid;Yuqi Liu;Hua Wang
{"title":"A Wideband Calibration-Free D-Band Passive Phase Shifter With Frequency-Invariant Codes Over 24% Fractional Bandwidth","authors":"Basem Abdelaziz Abdelmagid;Yuqi Liu;Hua Wang","doi":"10.1109/LSSC.2025.3622233","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3622233","url":null,"abstract":"This work presents a compact 110–140 GHz bidirectional D-band passive phase shifter based on combining a 5-stage capacitively-loaded reflective-type PS (RTPS) with a wideband 0°/180° stage. The design achieves a 360° phase range with a resolution of 11.25°. By applying: 1) a wideband RTPS design methodology on the stage level; 2) frequency/switching-staggering techniques among the RTPS stages; and 3) a balun-staggering technique into the 0°/180° stage, the design achieves calibration-free operation with frequency-invariant codes over 24% fractional bandwidth (FBW). The design is implemented in GlobalFoundaries 22-nm CMOS FD-SOI technology with a compact core area of <inline-formula> <tex-math>$130~mu $ </tex-math></inline-formula>m <inline-formula> <tex-math>$times 480~mu $ </tex-math></inline-formula>m. It achieves measured RMS phase and magnitude errors lower than 2.38° and 0.63 dB, respectively, across the entire operating bandwidth using the same frequency-invariant codes.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"329-332"},"PeriodicalIF":2.0,"publicationDate":"2025-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145405265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 168 nW to 44.3 Mb/s Adaptable TRNG With 400 mV Attack-Resilient Hybrid RO Core 一个168 nW到44.3 Mb/s的可适应TRNG，带有400 mV抗攻击的混合RO核心
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-10-14 DOI: 10.1109/LSSC.2025.3621413
Berkay Özbek;Timothy G. Constandinou
{"title":"A 168 nW to 44.3 Mb/s Adaptable TRNG With 400 mV Attack-Resilient Hybrid RO Core","authors":"Berkay Özbek;Timothy G. Constandinou","doi":"10.1109/LSSC.2025.3621413","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3621413","url":null,"abstract":"This letter presents an adaptable ring oscillator (RO)-true random number generator (TRNG) that removes the fixed power–throughput tradeoff by selecting delay-cell physics at run time. A hybrid core uses a current-starved inverter in low-power (LP) mode to amplify slew-limited jitter for high bit-efficiency at low frequency, and a latched cross-coupled cell in high-performance (HP) mode to exploit regeneration-time jitter over a wider band; both share a unified fast-by-slow sampling path with XOR combining. Fabricated in 180 nm CMOS (<inline-formula> <tex-math>$265times 490~mu $ </tex-math></inline-formula>m), the TRNG spans 0.8–2.0 V and <inline-formula> <tex-math>$- 20~^{circ }$ </tex-math></inline-formula>C–<inline-formula> <tex-math>$80~^{circ }$ </tex-math></inline-formula>C, achieves 168 nW (3.95 pJ/bit) in LP and 44.3 Mb/s in HP, and reaches near-ideal HP entropy (0.999999999984). Long datasets pass NIST SP 800-22 (including under 400 mV injection at the second harmonic), SP 800-90B, and AIS31. A single, digitally-tunable IP thus delivers nanowatt standby entropy and burst-mode throughput without architectural change.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"325-328"},"PeriodicalIF":2.0,"publicationDate":"2025-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145351895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A RISC-V SoC With Reconfigurable Custom Instructions on a Synthesized eFPGA Fabric in 22nm FinFET 在22nm FinFET合成eFPGA结构上具有可重构自定义指令的RISC-V SoC
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2025-10-07 DOI: 10.1109/LSSC.2025.3618942
Prashanth Mohan;Siddharth Das;Ken Mai
{"title":"A RISC-V SoC With Reconfigurable Custom Instructions on a Synthesized eFPGA Fabric in 22nm FinFET","authors":"Prashanth Mohan;Siddharth Das;Ken Mai","doi":"10.1109/LSSC.2025.3618942","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3618942","url":null,"abstract":"This letter presents a flexible and energy-efficient RISC-V system-on-chip (SoC) in 22nm FinFET technology, achieving state-of-the-art performance by tightly integrating the CPU with a synthesized embedded FPGA (embedded field programmable gate array (eFPGA)), enabling the implementation of reconfigurable custom instructions. The tight integration of the eFPGA with SoC scratchpad memory facilitates parallel high-bandwidth (16 GB/s) access to scratchpad SRAMs and enables rapid eFPGA reconfiguration (<inline-formula> <tex-math>$2~mu $ </tex-math></inline-formula>s) to switch between custom instruction sets. The eFPGA fabric itself is optimized for compute-intensive tasks, featuring fused logic tiles that amortize routing overheads to achieve a compute density of 22.3 GOPS/mm2. The measurement results from the fabricated chip demonstrate a peak energy efficiency of 748 GOPS/W (INT8) while improving throughput and energy by 1-2 orders of magnitude compared to the CPU for accelerated applications.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"321-324"},"PeriodicalIF":2.0,"publicationDate":"2025-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145351924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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