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IEEE Solid-State Circuits Letters最新文献

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A PVT-Tolerant STR-Based TRNG in 4-nm Achieving 60 Mbp/s and Its Performance Analysis via Mathematical Modeling 在 4 纳米工艺中实现 60 Mbp/s 的基于 STR 的 PVT 容限 TRNG 及其数学建模性能分析
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-06-26 DOI: 10.1109/LSSC.2024.3419722
Jieun Park;Yong Ki Lee;Karpinskyy Bohdan;Yunhyeok Choi;Jonghoon Shin;Hyo-Gyuem Rhew;Jongshin Shin
{"title":"A PVT-Tolerant STR-Based TRNG in 4-nm Achieving 60 Mbp/s and Its Performance Analysis via Mathematical Modeling","authors":"Jieun Park;Yong Ki Lee;Karpinskyy Bohdan;Yunhyeok Choi;Jonghoon Shin;Hyo-Gyuem Rhew;Jongshin Shin","doi":"10.1109/LSSC.2024.3419722","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3419722","url":null,"abstract":"This letter presents a high-performance true random number generator (TRNG) based on self-timed ring (STR), showing robust tolerance to PVT variations. The evaluations were performed over 320 chips (64 chips per process corner of nn, ff, ss, sf, and fs) across three voltages (0.75 V, 0.75 V±10%) and three temperatures (\u0000<inline-formula> <tex-math>$- 40~^{circ }$ </tex-math></inline-formula>\u0000C, \u0000<inline-formula> <tex-math>$25~^{circ }$ </tex-math></inline-formula>\u0000C, and \u0000<inline-formula> <tex-math>$150~^{circ }$ </tex-math></inline-formula>\u0000C). All 320 test chips demonstrated stable random generation at 60 Mb/s over all the test combinations without a single failure. The verification utilized a TRNG BIST, ensuring a minimum of 0.5 min-entropy per bit. Moreover, a mathematical model for the proposed TRNG is developed to derive the throughput and the entropy of the random output.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"255-258"},"PeriodicalIF":2.2,"publicationDate":"2024-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142276462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 44.3 TOPS/W SRAM Compute-in-Memory With Near-CIM Analog Memory and Activation for DAC/ADC-Less Operations 具有近 CIM 模拟存储器的 44.3 TOPS/W SRAM 存贮器计算功能，可激活无 DAC/ADC 操作
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-06-24 DOI: 10.1109/LSSC.2024.3418099
Peiyu Chen;Meng Wu;Wentao Zhao;Yufei Ma;Tianyu Jia;Le Ye
{"title":"A 44.3 TOPS/W SRAM Compute-in-Memory With Near-CIM Analog Memory and Activation for DAC/ADC-Less Operations","authors":"Peiyu Chen;Meng Wu;Wentao Zhao;Yufei Ma;Tianyu Jia;Le Ye","doi":"10.1109/LSSC.2024.3418099","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3418099","url":null,"abstract":"In this letter, we present an analog compute-in-memory (CIM) macro design which incorporates near-CIM analog memory and nonlinearity activation unit (NAU) to alleviate the DAC/ADC power bottleneck. Fully differential analog memory is designed with switched capacitor storage circuits. Activation function, e.g., rectified linear unit, is also performed in analog domain in NAU. The CIM macro is fabricated using TSMC 55-nm technology, with a peak macro-level efficiency of 44.3 TOPS/W and a system energy efficiency of 27.7 TOPS/W for analog input and output with 4-bit weight. The near-CIM analog memory and NAU solution brings 76.0% energy reduction compared with DAC/ADC solution, which contributes \u0000<inline-formula> <tex-math>$1.34times $ </tex-math></inline-formula>\u0000 to \u0000<inline-formula> <tex-math>$2.37times $ </tex-math></inline-formula>\u0000 energy efficiency improvement.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"299-302"},"PeriodicalIF":2.2,"publicationDate":"2024-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142430727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 620-pF-Compensated Dual-Mode Capacitance Readout IC for Subdisplay Panel Applications 用于副显示面板应用的 620-pF 补偿双模电容读出集成电路
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-06-24 DOI: 10.1109/LSSC.2024.3418523
Hamin Lee;Juwon Ham;Junmin Lee;Wooseok Jang;Seunghoon Ko
{"title":"A 620-pF-Compensated Dual-Mode Capacitance Readout IC for Subdisplay Panel Applications","authors":"Hamin Lee;Juwon Ham;Junmin Lee;Wooseok Jang;Seunghoon Ko","doi":"10.1109/LSSC.2024.3418523","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3418523","url":null,"abstract":"This letter presents a touch readout integrated circuit (IC) integrating both mutual- and self-capacitance sensing capabilities. The proposed IC aims to compensate for self-capacitance up to 620 pF by employing a combination of current-mode and capacitive-mode compensation techniques. A noise-monitoring scheme, based on the orthogonality of multicapacitance driving sequences, enhances readout performance by selectively detecting external noises during mutual-capacitance sensing operation. The IC achieved the measured signal-to-noise ratio (SNR) of 47.3, 30.6, and 36.1 dB in mutual-capacitance sensing and self-capacitance sensing of T/RX electrodes, respectively. By applying the noise-monitoring scheme, a 7-times higher noise power compared to the absence of external noise were successfully detected.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"195-198"},"PeriodicalIF":2.2,"publicationDate":"2024-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141964919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 2-to-10-b Output Precision Reconfigurable Compute-In-Memory Macro Leveraging Input Conditioning Using Residue Amplification 利用残差放大进行输入调节的 2-10-b 输出精度可重构内存计算巨集
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-06-17 DOI: 10.1109/LSSC.2024.3415476
Balaji Vijayakumar;Ashwin Balagopal Sundar;Janakiraman Viraraghavan;Varchas Bharadwaj
{"title":"A 2-to-10-b Output Precision Reconfigurable Compute-In-Memory Macro Leveraging Input Conditioning Using Residue Amplification","authors":"Balaji Vijayakumar;Ashwin Balagopal Sundar;Janakiraman Viraraghavan;Varchas Bharadwaj","doi":"10.1109/LSSC.2024.3415476","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3415476","url":null,"abstract":"Artificial intelligence workloads demand a wide range of multiply and accumulate (MAC) precision. Pitch-matching constraints in compute-in-memory (CIM) engines limit the analog-to-digital converter (ADC) precision to about 8 bits. This letter demonstrates a method of mapping a suitable input conditioned MAC range to the input dynamic range of the on-chip 7-b ADC, thereby achieving up to 10 bits of output MAC precision. A 424 Kb SRAM CIM macro was fabricated in TSMC 28 nm, which computes 72 MACs in parallel per cycle. Measurement results at nominal supply voltage show an energy efficiency of 196.6–102 TOPS/W/b for a 2–10 bit output MAC precision. Inference results on MNIST, CIFAR10, and CIFAR100 are shown with \u0000<inline-formula> <tex-math>$leq 1%$ </tex-math></inline-formula>\u0000 accuracy loss from the software baseline.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"219-222"},"PeriodicalIF":2.2,"publicationDate":"2024-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141991495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An 81.5dB SNDR, 2.5 MHz Bandwidth Incremental Continuous-Time Delta-Sigma ADC in 180 nm CMOS 采用 180 纳米 CMOS 的 81.5dB SNDR、2.5 MHz 带宽增量式连续时间三角积分 ADC
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-06-11 DOI: 10.1109/LSSC.2024.3412634
Aswani Kumar Unnam;Paramita Banerjee;Nagendra Krishnapura
{"title":"An 81.5dB SNDR, 2.5 MHz Bandwidth Incremental Continuous-Time Delta-Sigma ADC in 180 nm CMOS","authors":"Aswani Kumar Unnam;Paramita Banerjee;Nagendra Krishnapura","doi":"10.1109/LSSC.2024.3412634","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3412634","url":null,"abstract":"Adapting a continuous time delta-sigma analog-to-digital converter (ADC) for incremental operation at high sampling rates degrades the noise and distortion due to potential overload of the modulator as it comes out of reset and nonlinear residue on the reset switch due to input current flowing through it in the reset phase. It is shown that the input and DAC currents must simultaneously begin to flow through the first integrating capacitor to minimize the possibility of overload. The first integrator reset has to be released just before the start of the DAC pulse. A feedforward path must be used to ensure that the DAC output is close to the input signal from the beginning. Blocking the input current from flowing through the reset switch in the reset phase eliminates the effect of the nonlinear residue. A 320 MS/s fourth-order incremental delta-sigma ADC prototype in an 180nm process using the above techniques has 90 dB dynamic range, 82 dB SNDR, and 84.5 dB SNR in a 2.5 MHz bandwidth. It consumes 46.3 mW from a 1.8V supply and occupies 0.7 mm2.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"191-194"},"PeriodicalIF":2.2,"publicationDate":"2024-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141618102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 500-V, 6.25-MHz GaN-IC With Gate Driver and Level Shifter for Off-Line Power Supplies 用于离线电源的 500V、6.25MHz GaN-IC，带栅极驱动器和电平转换器
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-06-07 DOI: 10.1109/LSSC.2024.3411390
Niklas Deneke;Bernhard Wicht
{"title":"A 500-V, 6.25-MHz GaN-IC With Gate Driver and Level Shifter for Off-Line Power Supplies","authors":"Niklas Deneke;Bernhard Wicht","doi":"10.1109/LSSC.2024.3411390","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3411390","url":null,"abstract":"Gallium Nitride (GaN) technology enables essential progress in energy efficiency and density, especially in off-line power supplies. This letter presents a monolithic GaN-IC, including a half-bridge, formed by two high-voltage power FETs with respective gate drivers and a high-voltage level shifter, forming a signal interface between high-side and low-side domain, making use of a GaN-on-SOI technology. Verified by experimental results, it achieves 500-V switching at 6.25 MHz and is thus well suited for off-line power supplies.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"207-210"},"PeriodicalIF":2.2,"publicationDate":"2024-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141964881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 33V to 1V Ripple-Less Buck Converter With the Inverted AC Current Replica Circuit and Sub-0.5% Output Ripple for 5G Low Earth Orbit Application 一种 33V 至 1V 无纹波降压转换器，具有反向交流电流复制电路和低于 0.5% 的输出纹波，适用于 5G 低地球轨道应用
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-06-05 DOI: 10.1109/LSSC.2024.3410034
Yi-Hsiang Kao;Jie-Lin Wu;Chih-Cherng Liao;Hui-Hsuan Chang;Wei-Cheng Huang;Hsing-Yen Tsai;Rong-Bin Guo;Ke-Horng Chen;Kuo-Lin Zeng;Ying-Hsi Lin;Shian-Ru Lin;Tsung-Yen Tsai
{"title":"A 33V to 1V Ripple-Less Buck Converter With the Inverted AC Current Replica Circuit and Sub-0.5% Output Ripple for 5G Low Earth Orbit Application","authors":"Yi-Hsiang Kao;Jie-Lin Wu;Chih-Cherng Liao;Hui-Hsuan Chang;Wei-Cheng Huang;Hsing-Yen Tsai;Rong-Bin Guo;Ke-Horng Chen;Kuo-Lin Zeng;Ying-Hsi Lin;Shian-Ru Lin;Tsung-Yen Tsai","doi":"10.1109/LSSC.2024.3410034","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3410034","url":null,"abstract":"The proposed ripple-less buck converter (RLBC) uses a two-phase topology with an inverted ac current replica (IACCR) circuit to reduce output voltage ripple to meet the error vector magnitude (EVM) requirement of 5G new radio (5G NR) low earth orbit (LEO) application. Assistance inductance (AI) circuit emulates inductor current to avoid using extra inductors. Ripple minimization (RM) circuit further reduces output ripple by synchronizing the switching moment of power MOSFETs. Therefore, the proposed RLBC achieves 5G NR LEO standards with an EVM of -28.85dB.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"183-186"},"PeriodicalIF":2.2,"publicationDate":"2024-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141474854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
New Rectification Technique Employing Auxiliary Rectifier for Resonance Control Achieving Compact Size and High Efficiency in CMOS 采用辅助整流器进行谐振控制的新型整流技术，在 CMOS 中实现紧凑尺寸和高效率
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-06-05 DOI: 10.1109/LSSC.2024.3409710
Babita Gyawali;Ramesh K. Pokharel;Samundra K. Thapa;Adel Barakat;Naoki Shinohara
{"title":"New Rectification Technique Employing Auxiliary Rectifier for Resonance Control Achieving Compact Size and High Efficiency in CMOS","authors":"Babita Gyawali;Ramesh K. Pokharel;Samundra K. Thapa;Adel Barakat;Naoki Shinohara","doi":"10.1109/LSSC.2024.3409710","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3409710","url":null,"abstract":"This article presents the design and realization of a compact size high-efficiency complementary metal-oxide- semiconductor rectifier with resonance control technique employing the concept of parallel rectifier. The methodology involves the integration of two rectifiers, where one is main rectifier, specifically designated for rectification purposes and the other is auxiliary, serves for impedance matching, resulting in no matching at input. Furthermore, the auxiliary rectifier offers control over resonance of the proposed rectifier. The proposed design achieves more than 40% conversion efficiency at 22 dBm of input power for the broadband range from 2.4 to 3.5 GHz, with an active circuit size of \u0000<inline-formula> <tex-math>$0.21~mathrm {mm}^{2}$ </tex-math></inline-formula>\u0000.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"187-190"},"PeriodicalIF":2.2,"publicationDate":"2024-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141474849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A D-Band Wideband Single-Ended Neutralized Upconversion Mixer With Controlled LO Feedthrough in 65-nm CMOS 65 纳米 CMOS 中具有受控 LO 馈入的 D 波段宽带单端中和上转换混频器
IF 2.7
IEEE Solid-State Circuits Letters Pub Date : 2024-04-26 DOI: 10.1109/LSSC.2024.3393973
Chun Wang;Chenxin Liu;Hans Herdian;Abanob Shehata;Jill Mayeda;Kazuaki Kunihiro;Hiroyuki Sakai;Atsushi Shirane;Kenichi Okada
{"title":"A D-Band Wideband Single-Ended Neutralized Upconversion Mixer With Controlled LO Feedthrough in 65-nm CMOS","authors":"Chun Wang;Chenxin Liu;Hans Herdian;Abanob Shehata;Jill Mayeda;Kazuaki Kunihiro;Hiroyuki Sakai;Atsushi Shirane;Kenichi Okada","doi":"10.1109/LSSC.2024.3393973","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3393973","url":null,"abstract":"A D-band wideband passive single-ended upconversion mixer with controlled LO feedthrough in 65-nm CMOS process is presented in this letter. The LO feedthrough was controlled by the varactor and the neutralizing transmission line between the LO and RF ports of the mixer. In measurement, the proposed passive single-ended mixer had a conversion gain of −13.0±1.5 dB with an ultrawide 3-dB bandwidth from 110 to 160 GHz. The LO feedthrough suppression was from −38.9 to −24.4 dB at 135 GHz by changing the varactor bias. The measured OP1dB was −12.5 dBm at center frequency. The chip occupies 0.35 mm2, including pads.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"167-170"},"PeriodicalIF":2.7,"publicationDate":"2024-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141078836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
GaN Power Switch for Power Distribution Protection 用于配电保护的 GaN 电源开关
IF 2.7
IEEE Solid-State Circuits Letters Pub Date : 2024-04-10 DOI: 10.1109/LSSC.2024.3386870
Ronald Hassib Galvis Chacón;José Alexandre Diniz;Saulo Finco
{"title":"GaN Power Switch for Power Distribution Protection","authors":"Ronald Hassib Galvis Chacón;José Alexandre Diniz;Saulo Finco","doi":"10.1109/LSSC.2024.3386870","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3386870","url":null,"abstract":"The electrical power system (EPS) of satellites requires protection devices to isolate failures in short-circuit conditions that can occur in payloads due to various sources, such as debris, mishandling, or radiation. Latching current limiter (LCL) implemented with a pMOS power transistor is typically used for this task. Radiation can also affect the function of the LCL and compromise the mission of the satellite. Therefore, to improve radiation hardness, LCLs have been developed using different rad-hard techniques, such as the implementation of Wide BandGap (WBG) semiconductors as power switches. Gallium nitride (GaN) transistors are more resistant to radiation due to their intrinsic characteristics. In this letter, an LCL topology with a GaN power switch is presented to improve system reliability for space applications. The LCL has an integrated control circuit in 0.18\u0000<inline-formula> <tex-math>$mu text{m}$ </tex-math></inline-formula>\u0000 CMOS technology powered by an auxiliary source. The proposed LCL was validated by simulation and experimental tests. The LCL limited the current to the set value for a supply voltage of up to 50V and maintained a recovery time of less than 50\u0000<inline-formula> <tex-math>$mu text{s}$ </tex-math></inline-formula>\u0000, under short-circuit tests.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"155-158"},"PeriodicalIF":2.7,"publicationDate":"2024-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140813919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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