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IEEE Solid-State Circuits Letters最新文献

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A 5,000,000 Frame/Sec Burst-Mode Cryogenic Thermal Imager With On-Chip Frame Memory 带片上帧存储器的 5,000,000 帧/秒突发模式低温热成像仪
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-08-14 DOI: 10.1109/LSSC.2024.3443744
Xiaoyu Lian;Eric Stang;Kangping Hu;Pradeep R. Guduru;Jacob K. Rosenstein
{"title":"A 5,000,000 Frame/Sec Burst-Mode Cryogenic Thermal Imager With On-Chip Frame Memory","authors":"Xiaoyu Lian;Eric Stang;Kangping Hu;Pradeep R. Guduru;Jacob K. Rosenstein","doi":"10.1109/LSSC.2024.3443744","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3443744","url":null,"abstract":"This letter presents a high-speed global-shutter thermal imaging system, with a \u0000<inline-formula> <tex-math>$24^{V} times 24^{H} $ </tex-math></inline-formula>\u0000 pixel HgCdTe infrared focal plane array (FPA) detector and a custom CMOS readout integrated circuit (ROIC), including a 768-frame on-chip analog burst memory bank. Each pixel contains a buffered current injection circuit and a background current reduction circuit. The system is designed for cryogenic operation at liquid nitrogen temperatures, and it achieves a maximum burst-mode frame rate of five million frames per second, which is the fastest demonstrated imaging array for mid/long-wavelength infrared.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"235-238"},"PeriodicalIF":2.2,"publicationDate":"2024-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142099832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 250-Mb/s On-Chip Capacitive Digital Isolator With Adaptive Frequency Control 具有自适应频率控制功能的 250 Mb/s 片上电容式数字隔离器
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-08-06 DOI: 10.1109/LSSC.2024.3439534
Dongfang Pan;Zhiyong Xiong;Qiming Lu;Fangting Miao;Litao Wu;Lin Cheng
{"title":"A 250-Mb/s On-Chip Capacitive Digital Isolator With Adaptive Frequency Control","authors":"Dongfang Pan;Zhiyong Xiong;Qiming Lu;Fangting Miao;Litao Wu;Lin Cheng","doi":"10.1109/LSSC.2024.3439534","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3439534","url":null,"abstract":"In this letter, a fully integrated capacitive-coupled digital isolator is proposed. By utilizing the adaptive carrier frequency control (AFC) scheme, the power consumption at low data rate is significantly reduced while maintaining a maximum data rate of 250 Mb/s. The on-chip isolation capacitor provides 2.5-kVRMS isolation rating with compact silicon area. The transmitter (TX) and receiver (RX) are fabricated in a 180-nm CMOS technology. Measurement results show that the transmitter consumes 0.6 and 1.15 mA at 100 kb/s and 250 Mb/s, respectively.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"231-234"},"PeriodicalIF":2.2,"publicationDate":"2024-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141993931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An 8 Gb/s Far-End Crosstalk Cancelation and FFE Co-Designed TX Output Driver 8 Gb/秒远端串音消除和 FFE 协同设计 TX 输出驱动器
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-08-06 DOI: 10.1109/LSSC.2024.3439399
Guan-Yu Chen;Tai-Cheng Lee
{"title":"An 8 Gb/s Far-End Crosstalk Cancelation and FFE Co-Designed TX Output Driver","authors":"Guan-Yu Chen;Tai-Cheng Lee","doi":"10.1109/LSSC.2024.3439399","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3439399","url":null,"abstract":"This letter describes a single-ended transmitter (TX) output driver, which combines a feed-forward equalizer (FFE) and a far-end crosstalk (FEXT) canceller. The proposed output driver reduces the crosstalk-induced jitter (CIJ) between the two parallel coupled microstrip lines while preserving the inherent high-frequency boosting signal for the channel loss compensation. A prototype operating at a supply voltage of 0.9 V was fabricated in a 28-nm CMOS technology, occupying an area of \u0000<inline-formula> <tex-math>$0.025~{text {mm}^{2}}$ </tex-math></inline-formula>\u0000. This prototype reduces the peak-to-peak jitter and CIJ by 48% (29 ps) and 114%, respectively, at 8 Gb/s. Furthermore, it increases the horizontal eye-opening (BER < 1E-12) by 34%, with an energy efficiency of 1.08 pJ/bit/channel.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"227-230"},"PeriodicalIF":2.2,"publicationDate":"2024-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141993901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Asynchronous CMOS Current Readout With 124-dB Dynamic Range for Bioluminescence Sensing 用于生物发光传感、动态范围达 124 分贝的异步 CMOS 电流读出器
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-08-02 DOI: 10.1109/LSSC.2024.3437771
Muhammad Asfandyar Awan;Khalil Ahmad;Amine Bermak;Kabir H. Biswas;Bo Wang
{"title":"An Asynchronous CMOS Current Readout With 124-dB Dynamic Range for Bioluminescence Sensing","authors":"Muhammad Asfandyar Awan;Khalil Ahmad;Amine Bermak;Kabir H. Biswas;Bo Wang","doi":"10.1109/LSSC.2024.3437771","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3437771","url":null,"abstract":"This letter presents a photocurrent readout for bioluminescence detection. The design incorporates an asynchronous architecture employing a proposed capacitive feedback transimpedance amplifier (C-TIA) with a self-timed reset network and an all-digital reconfigurable time-domain quantization scheme. It eliminates the need for a periodic reset signal required in conventional C-TIAs and offers a wide dynamic range (DR) of 124 dB, a nonlinearity of 1.7%, and a 1-pArms input-referred noise while drawing only \u0000<inline-formula> <tex-math>$210~mu $ </tex-math></inline-formula>\u0000A from a 1.8-V supply. Fabricated in a standard 180-nm CMOS technology, it occupies an area of 0.16 mm2. This design aims to facilitate in vitro NanoLuc (NLuc) luciferase-based bioluminescence sensing for biomolecule quantification at room temperature, with preliminary biological testing presented in this letter.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"223-226"},"PeriodicalIF":2.2,"publicationDate":"2024-08-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141991494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 42.3 μm² Band to Band Tunneling-Based Oscillator Enabled Temperature to Digital Converter With Resolution FoM of 0.16 pJK² for Embedded Temperature Sensing 基于带对带隧道振荡器的 42.3 μm² 温度数字转换器，分辨率 FoM 为 0.16 pJK²，适用于嵌入式温度传感器
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-07-25 DOI: 10.1109/LSSC.2024.3433610
Abhishek A. Kadam;Shubham Patil;Ajay K. Singh;Maryam Shojaei Baghini;Udayan Ganguly;Laxmeesha Somappa
{"title":"A 42.3 μm² Band to Band Tunneling-Based Oscillator Enabled Temperature to Digital Converter With Resolution FoM of 0.16 pJK² for Embedded Temperature Sensing","authors":"Abhishek A. Kadam;Shubham Patil;Ajay K. Singh;Maryam Shojaei Baghini;Udayan Ganguly;Laxmeesha Somappa","doi":"10.1109/LSSC.2024.3433610","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3433610","url":null,"abstract":"In advanced high-speed integrated systems, the widely distributed and proliferation of temperature sensors to detect hotspots improve the robustness and reliability of the system by preventing overheating. Low area and low energy consumption are essential for integrated temperature sensors in such applications. The fabricated oscillator has a ten times less footprint than state-of-the-art temperature sensing cores (\u0000<inline-formula> <tex-math>$42.3~mu {mathrm { m}}^{2} $ </tex-math></inline-formula>\u0000) and enables low energy temperature to the digital converter (0.32 nJ energy/conversion) in GF45RFSOI technology. The proposed oscillator facilitates an area and energy-efficient temperature sensor (20 °C to 90 °C) with a simple counter-based digital readout with a best-in-class resolution figure of merit of 0.16 pJK2.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"215-218"},"PeriodicalIF":2.2,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141966120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 7-b 76-mW 40-GS/s Hybrid Voltage/Time-Domain ADC With Common-Mode Input Tracking 具有共模输入跟踪功能的 7-b 76-mW 40-GS/s 混合电压/时域 ADC
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-07-18 DOI: 10.1109/LSSC.2024.3430851
Amy Whitcombe;Somnath Kundu;Hariprasad Chandrakumar;Abhishek Agrawal;Thomas Brown;Steven Callender;Brent Carlton;Stefano Pellerano
{"title":"A 7-b 76-mW 40-GS/s Hybrid Voltage/Time-Domain ADC With Common-Mode Input Tracking","authors":"Amy Whitcombe;Somnath Kundu;Hariprasad Chandrakumar;Abhishek Agrawal;Thomas Brown;Steven Callender;Brent Carlton;Stefano Pellerano","doi":"10.1109/LSSC.2024.3430851","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3430851","url":null,"abstract":"High-speed links require fast, moderate resolution analog-to-digital converters (ADCs) with low power to maximize efficiency. Hybrid voltage and time (V+T) ADCs can combine the speed benefits of time-domain conversion with the reliability of conventional voltage-domain ADCs. This letter demonstrates 1) how the V+T architecture can simplify time interleaving implementation and 2) highlights two methods for improving V+T sub-ADC robustness: a) a voltage-to-time converter (VTC) with common-mode input voltage tracking and b) a merged time-to-voltage and flash time-to-digital converter. This is demonstrated in a 0.103-mm2 22-nm CMOS prototype that consumes 76 mW and gives 32.3-dB SNDR with a Nyquist input at 40 GS/s, for 57-fJ/step FoMw.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"211-214"},"PeriodicalIF":2.2,"publicationDate":"2024-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141966121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 2-Way W-Band Power Amplifier With an Isolated Combining Output Network for Power Back-Off Efficiency Enhancement in 16-nm FinFet Technology 一款采用 16 纳米 FinFet 技术的双路 W 波段功率放大器，带有隔离式组合输出网络，可提高功率衰减效率
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-07-10 DOI: 10.1109/LSSC.2024.3426336
Yahia Ibrahim;Ali Niknejad
{"title":"A 2-Way W-Band Power Amplifier With an Isolated Combining Output Network for Power Back-Off Efficiency Enhancement in 16-nm FinFet Technology","authors":"Yahia Ibrahim;Ali Niknejad","doi":"10.1109/LSSC.2024.3426336","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3426336","url":null,"abstract":"This letter introduces a W-Band sequential power amplifier (PA) (Lehmann and Knoechel, 2008) with a novel output network designed to minimize passive and combiner losses, while reducing the overall footprint compared to conventional sequential and Doherty PAs (Doherty, 1936). An isolated output combiner sums two PAs operating in two different modes: 1) the main amplifier operates in class AB and 2) the auxiliary amplifier operates in class C. The measured PA achieves a saturated output power \u0000<inline-formula> <tex-math>$(mathbf {P_{mathrm { sat}}})$ </tex-math></inline-formula>\u0000 of 13 dBm and a gain of 12.5 dB with 3-dB bandwidth (BW) from 79.5 to 94.5 GHz. Additionally, it demonstrates a peak power-added efficiency (PAE) of 19.4% and a 14.6% PAE at 6-dB power back-off (PBO) at 87.5 GHz. Furthermore, the PA achieves a data rate of 12 Gb/s for a 16QAM signal with an average output power of 5 dBm, an average PAE of 10%, and an EVM (RMS) of -20 dB. The PA was fabricated in 16-nm FinFet technology with core area of 0.15 mm2. To the authors’ knowledge, this PA has the highest PAE at 6-dB PBO for CMOS PAs operating in the W-Band.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"203-206"},"PeriodicalIF":2.2,"publicationDate":"2024-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141964880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Ultrawide Load-Range Fast-Transient Output Capacitor-Less Digital LDO With Adaptive Gate Modulation and Droop Detection 具有自适应栅极调制和下拉检测功能的超宽负载范围快速瞬态输出无电容数字 LDO
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-06-27 DOI: 10.1109/LSSC.2024.3420117
Gunmo Koo;Jaejin Kim;Seongmin Lee;Jae Hoon Shim;Kunhee Cho
{"title":"An Ultrawide Load-Range Fast-Transient Output Capacitor-Less Digital LDO With Adaptive Gate Modulation and Droop Detection","authors":"Gunmo Koo;Jaejin Kim;Seongmin Lee;Jae Hoon Shim;Kunhee Cho","doi":"10.1109/LSSC.2024.3420117","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3420117","url":null,"abstract":"An ultrawide load-range output capacitor-less digital LDO (DLDO) with an adaptive gate modulation scheme is described. The proposed DLDO is primarily regulated by digital codes with a synchronous clock signal while the gate driving level is dynamically adjusted according to the load current level. The proposed gate modulation scheme can significantly widen the dynamic range of load current and reduce the output voltage ripple. In addition, an asynchronous droop detection circuit, coupled with adaptive gate modulation, is added to improve the voltage droop and ensure fast recovery from load transients. The proposed DLDO was fabricated in 28-nm CMOS process. The dynamic load range of 57\u0000<inline-formula> <tex-math>$143times $ </tex-math></inline-formula>\u0000 (1.4–\u0000<inline-formula> <tex-math>$80~mu $ </tex-math></inline-formula>\u0000A) is achieved and the output voltage ripple of under 17 mV is measured across the entire load current range. A response time of less than 10 ns and a recovery time of less than 30 ns are measured in various load transient conditions.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"199-202"},"PeriodicalIF":2.2,"publicationDate":"2024-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141965281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A PVT-Tolerant STR-Based TRNG in 4-nm Achieving 60 Mbp/s and Its Performance Analysis via Mathematical Modeling 在 4 纳米工艺中实现 60 Mbp/s 的基于 STR 的 PVT 容限 TRNG 及其数学建模性能分析
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-06-26 DOI: 10.1109/LSSC.2024.3419722
Jieun Park;Yong Ki Lee;Karpinskyy Bohdan;Yunhyeok Choi;Jonghoon Shin;Hyo-Gyuem Rhew;Jongshin Shin
{"title":"A PVT-Tolerant STR-Based TRNG in 4-nm Achieving 60 Mbp/s and Its Performance Analysis via Mathematical Modeling","authors":"Jieun Park;Yong Ki Lee;Karpinskyy Bohdan;Yunhyeok Choi;Jonghoon Shin;Hyo-Gyuem Rhew;Jongshin Shin","doi":"10.1109/LSSC.2024.3419722","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3419722","url":null,"abstract":"This letter presents a high-performance true random number generator (TRNG) based on self-timed ring (STR), showing robust tolerance to PVT variations. The evaluations were performed over 320 chips (64 chips per process corner of nn, ff, ss, sf, and fs) across three voltages (0.75 V, 0.75 V±10%) and three temperatures (\u0000<inline-formula> <tex-math>$- 40~^{circ }$ </tex-math></inline-formula>\u0000C, \u0000<inline-formula> <tex-math>$25~^{circ }$ </tex-math></inline-formula>\u0000C, and \u0000<inline-formula> <tex-math>$150~^{circ }$ </tex-math></inline-formula>\u0000C). All 320 test chips demonstrated stable random generation at 60 Mb/s over all the test combinations without a single failure. The verification utilized a TRNG BIST, ensuring a minimum of 0.5 min-entropy per bit. Moreover, a mathematical model for the proposed TRNG is developed to derive the throughput and the entropy of the random output.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"255-258"},"PeriodicalIF":2.2,"publicationDate":"2024-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142276462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 44.3 TOPS/W SRAM Compute-in-Memory With Near-CIM Analog Memory and Activation for DAC/ADC-Less Operations 具有近 CIM 模拟存储器的 44.3 TOPS/W SRAM 存贮器计算功能，可激活无 DAC/ADC 操作
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-06-24 DOI: 10.1109/LSSC.2024.3418099
Peiyu Chen;Meng Wu;Wentao Zhao;Yufei Ma;Tianyu Jia;Le Ye
{"title":"A 44.3 TOPS/W SRAM Compute-in-Memory With Near-CIM Analog Memory and Activation for DAC/ADC-Less Operations","authors":"Peiyu Chen;Meng Wu;Wentao Zhao;Yufei Ma;Tianyu Jia;Le Ye","doi":"10.1109/LSSC.2024.3418099","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3418099","url":null,"abstract":"In this letter, we present an analog compute-in-memory (CIM) macro design which incorporates near-CIM analog memory and nonlinearity activation unit (NAU) to alleviate the DAC/ADC power bottleneck. Fully differential analog memory is designed with switched capacitor storage circuits. Activation function, e.g., rectified linear unit, is also performed in analog domain in NAU. The CIM macro is fabricated using TSMC 55-nm technology, with a peak macro-level efficiency of 44.3 TOPS/W and a system energy efficiency of 27.7 TOPS/W for analog input and output with 4-bit weight. The near-CIM analog memory and NAU solution brings 76.0% energy reduction compared with DAC/ADC solution, which contributes \u0000<inline-formula> <tex-math>$1.34times $ </tex-math></inline-formula>\u0000 to \u0000<inline-formula> <tex-math>$2.37times $ </tex-math></inline-formula>\u0000 energy efficiency improvement.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"299-302"},"PeriodicalIF":2.2,"publicationDate":"2024-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142430727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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