IEEE Solid-State Circuits Letters最新文献_第7页

A 0.015-mm2 0.5 -V Synthesizable Hybrid PLL With Multiphase Linear Proportional-Gain Paths 具有多相线性比例增益路径的0.015-mm2 0.5 v可合成混合锁相环

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IEEE Solid-State Circuits Letters Pub Date : 2025-12-29 DOI: 10.1109/LSSC.2025.3649215

Qibang Sun;Liqun Feng;Woogeun Rhee;Hanjun Jiang

引用次数: 0

A Broadband and Compact GaN Millimeter-Wave MMIC SPDT Switch Using Modified π-Networks 一种基于改进π网络的宽带紧凑型GaN毫米波MMIC SPDT开关

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IEEE Solid-State Circuits Letters Pub Date : 2025-12-22 DOI: 10.1109/LSSC.2025.3646815

Chaorong Wang;Quan Pan;Xiaohu Fang

{"title":"A Broadband and Compact GaN Millimeter-Wave MMIC SPDT Switch Using Modified π-Networks","authors":"Chaorong Wang;Quan Pan;Xiaohu Fang","doi":"10.1109/LSSC.2025.3646815","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3646815","url":null,"abstract":"This letter presents a design methodology for broadband and compact millimeter-wave (mm-wave) single-pole double-throw (SPDT) switches targeting the Ku–Ka band. Conventional SPDT switches based on quarter-wavelength transmission line typically occupy significant chip area, while alternative designs utilizing standard <inline-formula> <tex-math>$pi $ </tex-math></inline-formula>-type equivalent circuits often suffer from bandwidth degradation due to the parasitic inductance at the isolation path. To overcome these limitations, a novel SPDT architecture based on modified <inline-formula> <tex-math>$pi $ </tex-math></inline-formula>-networks is proposed. This approach incorporates the parasitic inductance of the isolation path into the <inline-formula> <tex-math>$pi $ </tex-math></inline-formula>-network design, effectively enhancing the bandwidth performance without increasing circuit complexity. For validation, an SPDT switch was implemented using a 0.15-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m GaN MMIC process, covering the 10–28 GHz band. Measurement results confirm that the switch achieves an insertion loss below 2.1 dB, return loss better than 12 dB and isolation greater than 42 dB, with a compact core chip area of only 0.62 mm2.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"21-24"},"PeriodicalIF":2.0,"publicationDate":"2025-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145886581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

220 GHz, 8.5-dBm Saturated Output Power Wideband Power Amplifier in SiGe BiCMOS 220ghz， 8.5 dbm SiGe BiCMOS饱和输出功率宽带功率放大器

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IEEE Solid-State Circuits Letters Pub Date : 2025-12-19 DOI: 10.1109/LSSC.2025.3646267

Xun Chen;Jonas Winkelhake;Muh-Dey Wei;Renato Negra

{"title":"220 GHz, 8.5-dBm Saturated Output Power Wideband Power Amplifier in SiGe BiCMOS","authors":"Xun Chen;Jonas Winkelhake;Muh-Dey Wei;Renato Negra","doi":"10.1109/LSSC.2025.3646267","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3646267","url":null,"abstract":"This letter presents a broadband <inline-formula> <tex-math>$G$ </tex-math></inline-formula>-band power amplifier (PA) designed in a 130-nm silicon-germanium (SiGe) bipolar complementary metal-oxide-semiconductor technology. Unlike dual-band matching and staggered tuning techniques to obtain large operation bandwidth (BW), we propose a common broadband amplification stage in this work for its flexibility. In each stage, inductive gain peaking is employed at the base terminal of the common-base (CB) transistor for BW extension. Meanwhile, the correlation between BW, inband gain and gain flatness is studied to determine the practical value of the inductance and AC decoupling capacitance. A current-mirror with thermal runaway protection is placed close to the amplifier in the implementation of each stage. The proposed PA achieves a peak small-signal gain of 27.6 dB over an operation BW from 140 to 238.7 GHz in measurements. The saturated output power, <inline-formula> <tex-math>$P_{text {sat}}$ </tex-math></inline-formula>, is 8.5 dBm at 220 GHz with a peak power-added efficiency (PAE) of 2.1%. The 3-dB <inline-formula> <tex-math>$P_{text {sat}}$ </tex-math></inline-formula> BW ranges from 150 to 220 GHz with fractional BW of 31.8% in measurements. To the best of the authors’ knowledge, the PA demonstrates the largest BW in <inline-formula> <tex-math>$G$ </tex-math></inline-formula>-band compared to other reported silicon-based PAs to date. Furthermore, the inband gain and output power over BW are easily adjustable based on system requirements due to the flexibility of the common broadband amplification stage.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"17-20"},"PeriodicalIF":2.0,"publicationDate":"2025-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11304730","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145886577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Actiniaria: Distributed Dynamic-IR-Drop-Aware Timing Monitor for AVFS With Lightweight Tentacles Actiniaria：分布式动态ir - drop - aware定时监视器与轻量级触角的AVFS

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IEEE Solid-State Circuits Letters Pub Date : 2025-12-17 DOI: 10.1109/LSSC.2025.3645701

Junyi Qian;Lishuo Deng;Cai Li;Yizhi Ding;Weiwei Shan

{"title":"Actiniaria: Distributed Dynamic-IR-Drop-Aware Timing Monitor for AVFS With Lightweight Tentacles","authors":"Junyi Qian;Lishuo Deng;Cai Li;Yizhi Ding;Weiwei Shan","doi":"10.1109/LSSC.2025.3645701","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3645701","url":null,"abstract":"Advances in integrated circuit (IC) technology have amplified the effects of process, voltage, and temperature (PVT) variations, particularly dynamic IR drop, which severely affects timing. Post-silicon IR drop monitoring circuits are lacking, forcing designers to reserve substantial static guard bands for worst-case scenarios, compromising energy efficiency. Inspired by biomimetics, this letter proposes an Actiniaria-shaped structure for distributed monitoring of multiple IR drop hotspots without invading critical paths (CPs). It comprises lightweight tentacles + central monitor. The tentacles use voltage-sensitive cells to sense the impact of IR drop on timing, while also supporting adaptive tuning for global variations. By using on-chip PVT sensors, Actiniaria tracks the timing characteristics of the longest CP in real time under PVT variations. A two-stage prewarning timing monitor captures timing margins and employs adaptive voltage/frequency scaling (AVFS) strategies to compress redundant guard bands. When applied to an open-source multicore RISC-V processor fabricated in 22-nm CMOS, Actiniaria achieves a 40.6% reduction in power consumption through noninvasive dynamic IR drop monitoring while having only 0.08% area overhead.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"25-28"},"PeriodicalIF":2.0,"publicationDate":"2025-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145929497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 28-nm FeFET Compute-in-Memory Macro With 64×64 Array Size and On-Chip 4-Bit Flash ADC 具有64×64阵列大小和片上4位闪存ADC的28纳米ffet内存宏计算

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IEEE Solid-State Circuits Letters Pub Date : 2025-12-03 DOI: 10.1109/LSSC.2025.3640522

Vaidehi Garg;Jianwei Jia;Omkar Phadke;Shimeng Yu

引用次数: 0

A 500 MS/s Robust 2b/cycle Pipelined-SAR ADC Achieving 64.6-dB SNDR and 82.6-dB SFDR With Linearity Enhancement Techniques 一种500 MS/s鲁棒2b/周期流水线sar ADC，通过线性增强技术实现64.6 db SNDR和82.6 db SFDR

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IEEE Solid-State Circuits Letters Pub Date : 2025-12-02 DOI: 10.1109/LSSC.2025.3639322

Qiang Yu;Zheng Zhu;Lulu Zhang;Qin Huang;Yao Feng;Chao Liang;Biao Hu;Ling Du;Rongbin Yang;Shuangyi Wu;Qiang Li

引用次数: 0

A 28-nm Digital Compute-in-Memory Ising Annealer With Asynchronous Random Number Generator for Traveling Salesman Problem 基于异步随机数生成器的28纳米内存计算退火算法研究旅行商问题

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IEEE Solid-State Circuits Letters Pub Date : 2025-12-01 DOI: 10.1109/LSSC.2025.3639178

Yuyao Kong;Haomei Liu;Vaidehi Garg;Shimeng Yu

{"title":"A 28-nm Digital Compute-in-Memory Ising Annealer With Asynchronous Random Number Generator for Traveling Salesman Problem","authors":"Yuyao Kong;Haomei Liu;Vaidehi Garg;Shimeng Yu","doi":"10.1109/LSSC.2025.3639178","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3639178","url":null,"abstract":"This work presents a compact digital compute-in-memory (DCIM) Ising annealer targeting large-scale combinatorial optimization. A centroid-based weight mapping method combined with hierarchical clustering reduces the memory capacity required for traveling salesman problem (TSP) weights, enabling efficient mapping with limited on-chip storage. An asynchronous random number generator (ARNG) based on dual ring oscillator provides high-quality randomness with tunable probability bias while incurring much smaller hardware overhead than conventional linear feedback shift registers (LFSRs). The proposed architecture was fabricated in 28-nm CMOS, integrating a DCIM array and an on-chip asynchronous-clock-based random number generator (ARNG). Measurement results demonstrate annealing on TSP problems up to 3038 cities. Compared to LFSR-based randomness, the ARNG achieves solution quality closer to the software baseline while maintaining compact area. This design highlights a scalable and energy-efficient hardware framework for Ising-based optimization, showing clear advantages in both memory efficiency and random source quality over prior approaches.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"1-4"},"PeriodicalIF":2.0,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145705914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 112-Gb/s PAM4 Receiver With a Phase Equalization AFE in 7-nm FinFET 带相位均衡AFE的7纳米FinFET 112-Gb/s PAM4接收机

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IEEE Solid-State Circuits Letters Pub Date : 2025-11-28 DOI: 10.1109/LSSC.2025.3637833

Huanan Guo;Yufeng Yao;Xiang Gao

引用次数: 0

A High-Speed D-FF and a 11-Bit Up-Down Counter Using Unipolar Oxide TFTs on a Flexible Foil 在柔性箔上使用单极氧化物tft的高速D-FF和11位上下计数器

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IEEE Solid-State Circuits Letters Pub Date : 2025-11-21 DOI: 10.1109/LSSC.2025.3636192

Suyash Shrivastava;Pydi Ganga Bahubalindruni

{"title":"A High-Speed D-FF and a 11-Bit Up-Down Counter Using Unipolar Oxide TFTs on a Flexible Foil","authors":"Suyash Shrivastava;Pydi Ganga Bahubalindruni","doi":"10.1109/LSSC.2025.3636192","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3636192","url":null,"abstract":"This manuscript presents an experimental characterization of a novel high speed D flip-flop (D-FF). The circuit was fabricated on a <inline-formula> <tex-math>$27mu $ </tex-math></inline-formula>m thick flexible polyimide substrate using a nMOS only, single gate amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistor (TFT) technology. Reliable response of the D-FF was noticed from measurements up to a clock and an input signal frequency of <inline-formula> <tex-math>$20{mathrm {,}}$ </tex-math></inline-formula>MHz and <inline-formula> <tex-math>$2{mathrm {,}}$ </tex-math></inline-formula>MHz, respectively. Further, with an output voltage swing of 60%, D-FF functionality was observed up to clock and input signal frequencies of <inline-formula> <tex-math>$25{mathrm {,}}$ </tex-math></inline-formula>MHz and <inline-formula> <tex-math>$3{mathrm {,}}$ </tex-math></inline-formula>MHz, respectively. This circuit has shown a power dissipation of <inline-formula> <tex-math>$140{mathrm {,}} mu $ </tex-math></inline-formula>W including buffers and the figure-of-merit (FOM) of <inline-formula> <tex-math>$142{mathrm {,}}$ </tex-math></inline-formula>MHz/mW, which is almost a 52% improvement compared to the state-of-the-art. In addition, this D-FF is employed in the implementation of an 11-bit up/down (U/D) counter. The U/D counter has shown a reliable operation up to an operating frequency of <inline-formula> <tex-math>$8{mathrm {,}}$ </tex-math></inline-formula>MHz with a power consumption of <inline-formula> <tex-math>$4.8{mathrm {,}}$ </tex-math></inline-formula>mW. Both circuits were characterized at a low supply voltage of <inline-formula> <tex-math>$3{mathrm {,}}$ </tex-math></inline-formula>V, occupying an active area of <inline-formula> <tex-math>$0.144{mathrm {,}}$ </tex-math></inline-formula>mm2 and <inline-formula> <tex-math>$4.32{mathrm {,}}$ </tex-math></inline-formula>mm2, respectively. These circuits would find potential application in biomedical wearable devices.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"373-376"},"PeriodicalIF":2.0,"publicationDate":"2025-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145674680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Advancing On-Cell Near-Field Monitoring for Thermal Runaway Detection in EV Batteries 电池内近场监测技术在电动汽车电池热失控检测中的应用

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IEEE Solid-State Circuits Letters Pub Date : 2025-11-18 DOI: 10.1109/LSSC.2025.3634340

Simon Foster;Scott Block;Daniel McMitchell;Edgar Colin-Beltran;Robert Dailey

引用次数: 0