IEEE Solid-State Circuits Letters最新文献_第7页

A 1.54 pJ/b 80 Gb/s D-Band 2-D Scalable Transceiver Array With On-Chip Antennas in 28-nm Bulk CMOS 基于28nm CMOS片上天线的1.54 pJ/b 80gb /s d波段二维可扩展收发器阵列

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2025-02-05 DOI: 10.1109/LSSC.2025.3539228

Hesham Beshary;Yikuan Chen;Ethan Chou;Ali M. Niknejad

{"title":"A 1.54 pJ/b 80 Gb/s D-Band 2-D Scalable Transceiver Array With On-Chip Antennas in 28-nm Bulk CMOS","authors":"Hesham Beshary;Yikuan Chen;Ethan Chou;Ali M. Niknejad","doi":"10.1109/LSSC.2025.3539228","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3539228","url":null,"abstract":"This work represents a 140 GHz wideband 2-D scalable phased array in 28-nm bulk CMOS technology. The chip integrates <inline-formula> <tex-math>$2times 2$ </tex-math></inline-formula> transceiving elements with on-chip antennas and a <inline-formula> <tex-math>$times 16$ </tex-math></inline-formula> LO multiplication chain in <inline-formula> <tex-math>$2.115times 2$ </tex-math></inline-formula>.115 mm2. The elements are forming an RF beamformer while keeping approximately half-wavelength spacing between the elements. The integrated antennas leverage substrate thinning and substrate mode cancellation to boost the array radiation efficiency. The system adopts a superheterodyne transceiver (TRX) architecture with 25 GHz IF center frequency. The proposed work achieves 1.54 pJ/b and 80 Gb/s over-the-air (OTA) using 16-QAM modulation scheme for the overall transmit-receive link. To the best of the authors’ knowledge, this work achieves the highest reported array-level OTA data rate while improving the energy efficiency (pJ/b) by approximately an order of magnitude compared to other D-band transceiver arrays.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"61-64"},"PeriodicalIF":2.2,"publicationDate":"2025-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143455321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

5-nm High-Efficiency and High-Density Digital SRAM In-Memory-Computing Macros for AI Accelerators 用于AI加速器的5nm高效高密度数字SRAM内存计算宏

IF 2

IEEE Solid-State Circuits Letters Pub Date : 2025-01-22 DOI: 10.1109/LSSC.2025.3532788

Seok-Ju Yun;Jaehyuk Lee;Sungmeen Myung;Jangho An;Daekun Yoon;Seungchul Jung;Soonwan Kwon;Sangjoon Kim

引用次数: 0

A 0.86 mW 17 fA/√Hz, 129-dB DR Current-Sensing Front-End for Under-Display Ambient Light Sensor With Zero-Compensated Logarithmic TIA 一种0.86 mW 17 fA/√Hz， 129 db DR电流传感前端，用于零补偿对数TIA显示下环境光传感器

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2025-01-13 DOI: 10.1109/LSSC.2025.3528962

Liheng Liu;Tianxiang Qu;Hao Li;Dan Li;Gan Guo;Zhiliang Hong;Jiawei Xu

{"title":"A 0.86 mW 17 fA/√Hz, 129-dB DR Current-Sensing Front-End for Under-Display Ambient Light Sensor With Zero-Compensated Logarithmic TIA","authors":"Liheng Liu;Tianxiang Qu;Hao Li;Dan Li;Gan Guo;Zhiliang Hong;Jiawei Xu","doi":"10.1109/LSSC.2025.3528962","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3528962","url":null,"abstract":"This letter presents a low-noise, power-efficient, and pulsatile-interference stabilized photocurrent readout circuit for under-display ambient light sensors (ALS). To achieve pA-level input noise and seven decades of input current dynamic range (DR) simultaneously, a logarithmic transimpedance amplifier (TIA) with a diode-connected MOS feedback is set as the first stage of the ALS. An auto-tracking zero, implemented in the amplifier of the TIA, improves the phase-margin and reduces the settling time against pulsatile interference without extra power consumption. The TIA output is then quantized by a first-order 9-bit incremental delta-sigma modulator. Fabricated in a standard 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS process, the proposed ALS achieves the best-in-the-class input-referred current noise of <inline-formula> <tex-math>$0.6~rm {pA}_{mathrm {rms}}$ </tex-math></inline-formula> within a 400-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>s readout time. The total input range of <inline-formula> <tex-math>$1.7~rm {pA}_{mathrm {PP}}$ </tex-math></inline-formula>–<inline-formula> <tex-math>$5~mu rm {A}_{mathrm {PP}}$ </tex-math></inline-formula> corresponds to a DR of 129 dB while consuming 0.86 mW at a 1.8-V supply.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"49-52"},"PeriodicalIF":2.2,"publicationDate":"2025-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143105874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

20–26-GHz CMOS PA With High Pout and OP1 dB Using a 1:2 Capacitance-Ratio-Equivalent Power Combiner 20 - 26 ghz高输出和OP1 dB的CMOS PA采用1:2电容比等效功率合成器

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2025-01-13 DOI: 10.1109/LSSC.2025.3529347

Jin-Fa Chang

{"title":"20–26-GHz CMOS PA With High Pout and OP1 dB Using a 1:2 Capacitance-Ratio-Equivalent Power Combiner","authors":"Jin-Fa Chang","doi":"10.1109/LSSC.2025.3529347","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3529347","url":null,"abstract":"We demonstrate a four-way wide-band power amplifier (PA1) with a 1:2 capacitance-ratio-equivalent power combiner (PC) and a dynamic-threshold-voltage MOSFET with a resistor (DTMOS-R) using a 90-nm CMOS. Another PA (PA2) without a DTMOS-R using low-loss micro-strip line inductors replaced with a PC is demonstrated for contrast. A low-loss PC is realized using equal <inline-formula> <tex-math>$lambda $ </tex-math></inline-formula>/4 spiral transmission line inductors based on a <inline-formula> <tex-math>$lambda $ </tex-math></inline-formula>/9 one (with a 1:2 capacitance ratio involving Cp1 and Cp2) for low-loss output-stage matching. The output power of the output stage of PA1, with low-threshold voltage (<inline-formula> <tex-math>$V_{mathrm { th}}$ </tex-math></inline-formula>) due to the DTMOS-R and low Rds based on the parallel four-way output, is enhanced using a PC. Between 20–26 GHz, PA1 achieves a prominent S21 of 23.2 dB, peak power-added-efficiency (PAE) between 20.8%–29.7%, and saturation output power between 19.9–21.2 dBm. Moreover, the output 1-dB compression point (OP1dB) is 16–20.4 dBm between 20–26 GHz. Using the PC and DTMOS-R yields the bulk CMOS PA’s high performance (Pout, PAE, and OP1dB), comparable to recent state-of-the-art millimeter-wave PAs, i.e., SOI/SiGe processes.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"53-56"},"PeriodicalIF":2.2,"publicationDate":"2025-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143105875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 23–28-GHz Doherty Power Amplifier With a PVT Insensitive Power Detection for Adaptive Biasing 基于PVT自适应偏置不敏感功率检测的23 - 28 ghz多尔蒂功率放大器

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2025-01-10 DOI: 10.1109/LSSC.2025.3528055

Yahia Ibrahim;Ali Niknejad

{"title":"A 23–28-GHz Doherty Power Amplifier With a PVT Insensitive Power Detection for Adaptive Biasing","authors":"Yahia Ibrahim;Ali Niknejad","doi":"10.1109/LSSC.2025.3528055","DOIUrl":"https://doi.org/10.1109/LSSC.2025.3528055","url":null,"abstract":"This letter presents a compact Doherty power amplifier (PA) featuring a single transformer balun. A novel envelope power detector architecture is introduced for high-bandwidth (BW) adaptive biasing, that is, insensitive to process-voltage–temperature (PVT) variations. The measured PA attains a saturated power <inline-formula> <tex-math>$(mathbf {P_{mathrm { sat}}})$ </tex-math></inline-formula> exceeding 20.2 dBm and a power gain of 19.5 dB across the frequency range of 23–28 GHz. Moreover, it exhibits a peak power added efficiency (PAE) of 38% and a 6-dB power back-off (PBO) PAE of 27% at 25 GHz. The proposed adaptive biasing scheme enables a modulation BW of up to 800 MHz for a 64-QAM signal. Under this setting, the average output power <inline-formula> <tex-math>$(mathbf {P_{avg}})$ </tex-math></inline-formula> is measured at 11.3 dBm with an RMS error vector magnitude (EVM) of −24.5 dB and an average PAE of 15.5%. The PA is fabricated in Global Foundries 45-nm-SOI technology with a compact area of 0.27 mm2. To the best of the authors’ knowledge, this work is the first to demonstrate robust performance for Doherty PAs across PVT variations.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"41-44"},"PeriodicalIF":2.2,"publicationDate":"2025-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143105950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Low-Jitter Fractional-N LC-PLL With a 1/4 DTC-Range-Reduction Technique 具有1/4 dtc范围缩减技术的低抖动分数n lc -锁相环

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2025-01-10 DOI: 10.1109/LSSC.2025.3528005

Gaofeng Jin;Fei Feng;Yan Chen;Hanli Liu;Xiang Gao

引用次数: 0

A Sub-THz Harmonic Recycling Single-Stage Frequency Quadrupler in CMOS 28-nm Technology 基于CMOS 28纳米技术的次太赫兹谐波回收单级四倍频器

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2025-01-09 DOI: 10.1109/LSSC.2025.3527533

Ali Ameri;Ali M. Niknejad

引用次数: 0

A 65-nm Delta-Sigma ADC-Based VDD-Variation-Tolerant Power-Side-Channel-Attack Sensor 一种65纳米Delta-Sigma adc型vdd容差功率侧信道攻击传感器

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2025-01-08 DOI: 10.1109/LSSC.2025.3527153

Shota Konno;Zachary J. Ellis;Anupam Golder;Sigang Ryu;Daniel Dinu;Avinash Varna;Sanu Mathew;Arijit Raychowdhury

引用次数: 0

A 1.1-pJ/b/Lane, 1.8-Tb/s Chiplet Using 113-Gb/s PAM-4 Transceiver With Equalization Strategy to Reduce Fractionally Spaced 0.5-UI ISI in 5-nm CMOS 基于113gb /s PAM-4收发器的1.1 pj /b/Lane 1.8 tb /s芯片及均衡策略降低分数间隔0.5 ui ISI

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2025-01-06 DOI: 10.1109/LSSC.2025.3526877

G. Gangasani;A. Mostafa;A. Singh;D. Storaska;D. Prabakaran;K. Mohammad;M. Baecher;M. Shannon;M. Sorna;M. Wielgos;P. Jenkins;P. Ramakrishna;U. Shukla

引用次数: 0

A 2.6-GS/s 8-bit Time-Interleaved ADC With Fully Dynamic Current Integrating Sampler 具有全动态电流积分采样器的2.6-GS/s 8位时间交错ADC

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2024-12-27 DOI: 10.1109/LSSC.2024.3523509

Dengquan Li;Maowen Qian;Depan Li;Hongzhi Liang;Zhangming Zhu

引用次数: 0