IEEE Solid-State Circuits Letters最新文献_第7页

A D-Band Wideband Single-Ended Neutralized Upconversion Mixer With Controlled LO Feedthrough in 65-nm CMOS 65 纳米 CMOS 中具有受控 LO 馈入的 D 波段宽带单端中和上转换混频器

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-04-26 DOI: 10.1109/LSSC.2024.3393973

Chun Wang;Chenxin Liu;Hans Herdian;Abanob Shehata;Jill Mayeda;Kazuaki Kunihiro;Hiroyuki Sakai;Atsushi Shirane;Kenichi Okada

引用次数: 0

GaN Power Switch for Power Distribution Protection 用于配电保护的 GaN 电源开关

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-04-10 DOI: 10.1109/LSSC.2024.3386870

Ronald Hassib Galvis Chacón;José Alexandre Diniz;Saulo Finco

{"title":"GaN Power Switch for Power Distribution Protection","authors":"Ronald Hassib Galvis Chacón;José Alexandre Diniz;Saulo Finco","doi":"10.1109/LSSC.2024.3386870","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3386870","url":null,"abstract":"The electrical power system (EPS) of satellites requires protection devices to isolate failures in short-circuit conditions that can occur in payloads due to various sources, such as debris, mishandling, or radiation. Latching current limiter (LCL) implemented with a pMOS power transistor is typically used for this task. Radiation can also affect the function of the LCL and compromise the mission of the satellite. Therefore, to improve radiation hardness, LCLs have been developed using different rad-hard techniques, such as the implementation of Wide BandGap (WBG) semiconductors as power switches. Gallium nitride (GaN) transistors are more resistant to radiation due to their intrinsic characteristics. In this letter, an LCL topology with a GaN power switch is presented to improve system reliability for space applications. The LCL has an integrated control circuit in 0.18\u0000<inline-formula> <tex-math>$mu text{m}$ </tex-math></inline-formula>\u0000 CMOS technology powered by an auxiliary source. The proposed LCL was validated by simulation and experimental tests. The LCL limited the current to the set value for a supply voltage of up to 50V and maintained a recovery time of less than 50\u0000<inline-formula> <tex-math>$mu text{s}$ </tex-math></inline-formula>\u0000, under short-circuit tests.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"155-158"},"PeriodicalIF":2.7,"publicationDate":"2024-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140813919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Ka-Band Mutual Coupling Resilient Stacked-FET Power Amplifier With 21.2 dBm OP1dB and 27.6% PAE1dB in 45-nm CMOS SOI 45 纳米 CMOS SOI 中具有 21.2 dBm OP1dB 和 27.6% PAE1dB 的 Ka 波段抗互耦叠加场效应晶体管功率放大器

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-04-10 DOI: 10.1109/LSSC.2024.3386676

Jian Zhang;Dawei Wang;Wei Zhu;Ming Zhai;Xiangjie Yi;Yan Wang

引用次数: 0

248-GHz Subharmonic Mixer Last Transmitter With I/Q Imbalance and LO Feedthrough Calibration 具有 I/Q 不平衡和 LO 馈入校准功能的 248-GHz 次谐波混频器末级发射机

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-04-10 DOI: 10.1109/LSSC.2024.3387285

Seunghoon Lee;Junhyeong Kim;Kangseop Lee;Ho-Jin Song

引用次数: 0

A Fully Integrated Digital LDO With Adaptive Sampling and Statistical Comparator Selection 具有自适应采样和统计比较器选择功能的全集成数字 LDO

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-04-04 DOI: 10.1109/LSSC.2024.3385233

Shun Yamaguchi;Takashi Hisakado;Osami Wada;Mahfuzul Islam

引用次数: 0

A Subthreshold Time-Domain Analog Spiking Neuron With PLL-Based Leak Circuit and Capacitive DAC Synapse 基于 PLL 泄漏电路和电容式 DAC 突触的阈下时域模拟尖峰神经元

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-04-04 DOI: 10.1109/LSSC.2024.3384762

Taylor Barton;Shea Smith;Yu Hao;Ryan Watson;Kyle Rogers;Parker Allred;Bibhu Datta Sahoo;Nancy Fulda;Jordan T. Yorgason;Karl F. Warnick;Mau-Chung Frank Chang;Yen-Cheng Kuan;Shiuh-Hua Wood Chiang

引用次数: 0

Design and Stability Analysis of the Variable-Sawtooth-Based PWM Controller for the AC-Coupled Envelope Tracking Supply Modulator 用于交流耦合包络跟踪电源调制器的基于可变锯齿的 PWM 控制器的设计和稳定性分析

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-04-02 DOI: 10.1109/LSSC.2024.3384345

Peng Xu;Tao Wang;Xueli Zhang;Peng Cao;Jiawei Xu;Zhiliang Hong

引用次数: 0

An 18-nW CMOS Current and Voltage Reference Circuit With Low Line Sensitivity and Wide Temperature Range 具有低线路灵敏度和宽温度范围的 18-nW CMOS 电流和电压基准电路

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2024-03-30 DOI: 10.1109/LSSC.2024.3407583

I-Fan Lin;Yu-Chu Tsai;Heng-Li Lin;Yu-Te Liao

{"title":"An 18-nW CMOS Current and Voltage Reference Circuit With Low Line Sensitivity and Wide Temperature Range","authors":"I-Fan Lin;Yu-Chu Tsai;Heng-Li Lin;Yu-Te Liao","doi":"10.1109/LSSC.2024.3407583","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3407583","url":null,"abstract":"This letter presents a design for a voltage and current reference (VCR) that utilizes a 0.18-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m CMOS process. The design employs stacked-diode MOS transistors (SDMTs) to generate a voltage that is complementary to absolute temperature for the current reference (CR). By adjusting the transistor size ratio, this bias voltage exhibits the similar temperature coefficient (TC) as that of the resistor in the CR. To enhance temperature compensation, a reversely biased transistor is employed in the voltage reference (VR). Additionally, the cascode current mirror and SDMTs in the VR mitigate supply sensitivity in both voltage and current outputs. The VCR achieves a TC of 124 ppm/°C in VR and 264 ppm/°C in CR over a temperature range of \u0000<inline-formula> <tex-math>$- 40~^{circ }$ </tex-math></inline-formula>\u0000C to \u0000<inline-formula> <tex-math>$130~^{circ }$ </tex-math></inline-formula>\u0000C. Furthermore, it achieves a line sensitivity of 0.011 %/V in VR and 0.094 %/V in CR while operating at 18.51 nW at room temperature. The active chip area of the VCR is approximately \u0000<inline-formula> <tex-math>$25~000~mu $ </tex-math></inline-formula>\u0000m2.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"179-182"},"PeriodicalIF":2.2,"publicationDate":"2024-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141474867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 23.9-μW 13.6-Bit Period Modulation-Based Capacitance-to-Digital Converter With Dynamic Current Mirror Front-End 带动态电流镜前端的 23.9μW 13.6 位基于周期调制的电容数字转换器

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-03-28 DOI: 10.1109/LSSC.2024.3382813

Hyeyeon Lee;Donguk Seo;Young-Jin Woo;Yoonmyung Lee;Inhee Lee;Youngcheol Chae

{"title":"A 23.9-μW 13.6-Bit Period Modulation-Based Capacitance-to-Digital Converter With Dynamic Current Mirror Front-End","authors":"Hyeyeon Lee;Donguk Seo;Young-Jin Woo;Yoonmyung Lee;Inhee Lee;Youngcheol Chae","doi":"10.1109/LSSC.2024.3382813","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3382813","url":null,"abstract":"This letter proposes a low-power high-precision capacitance-to-digital converter (CDC) utilizing a dynamic current mirror (DCM) to transform a sensor input capacitance \u0000<inline-formula> <tex-math>$(C_{mathrm{ IN}})$ </tex-math></inline-formula>\u0000 into an output current. The resulting current is directly proportional to the ratio of \u0000<inline-formula> <tex-math>$C_{mathrm{ IN}}$ </tex-math></inline-formula>\u0000 to an internal reference capacitor \u0000<inline-formula> <tex-math>$(C_{mathrm {REF}})$ </tex-math></inline-formula>\u0000 and subsequently converted into a period-modulated output, facilitating simple digitization by a digital counter. The CDC achieves an extensive \u0000<inline-formula> <tex-math>$C_{mathrm{ IN}}$ </tex-math></inline-formula>\u0000 range of 1 to 68 pF without the need for a power-hungry reference buffer. Fabricated in a 65-nm CMOS process, the prototype IC occupies a small area of 0.05-mm2 and consumes only \u0000<inline-formula> <tex-math>$23.9~mu text{W}$ </tex-math></inline-formula>\u0000 even with a \u0000<inline-formula> <tex-math>$C_{mathrm{ IN}}$ </tex-math></inline-formula>\u0000 of 47 pF. It achieves a capacitance resolution of 1.65 fF for a \u0000<inline-formula> <tex-math>$C_{mathrm{ IN}}$ </tex-math></inline-formula>\u0000 of 1 pF with a conversion time of 4 ms, corresponding to a 13.6-bit effective number of bit.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"135-138"},"PeriodicalIF":2.7,"publicationDate":"2024-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140606068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Compact Phase-Domain Delta–Sigma Time-to-Digital Converter With 8.5-ps Resolution for LiDAR Applications 用于激光雷达应用的 8.5 ps 分辨率紧凑型相位域三角积分时数字转换器

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-03-27 DOI: 10.1109/LSSC.2024.3382594

Yoondeok Na;Myung-Jae Lee;Youngcheol Chae

{"title":"A Compact Phase-Domain Delta–Sigma Time-to-Digital Converter With 8.5-ps Resolution for LiDAR Applications","authors":"Yoondeok Na;Myung-Jae Lee;Youngcheol Chae","doi":"10.1109/LSSC.2024.3382594","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3382594","url":null,"abstract":"This letter introduces a compact, high-resolution time-to-digital converter (TDC) for lidar applications. In contrast to a conventional histogram-based peak detection method, this letter proposes a mean detection method using a highly digitized phase-domain delta–sigma (PD\u0000<inline-formula> <tex-math>$Delta Sigma$ </tex-math></inline-formula>\u0000) TDC. The proposed TDC operates in an incremental \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000 manner for a compact implementation and utilizing a digital integrator as a loop filter that facilitates an extended counting, resulting in significantly improved resolution. By utilizing a dual gated-ring oscillator (GRO) structure, time-quantization noise due to a residue phase of GRO is effectively mitigated. To address the issue of single-photon avalanche diode (SPAD) signals due to their stochastic nature, a dual time window is proposed to compensate for counting error when SPAD trigger missing occurs. Fabricated in a 65-nm CMOS process, the prototype TDC occupies only an area of \u0000<inline-formula> <tex-math>$2000~mu text{m}~^{mathrm{ 2}}$ </tex-math></inline-formula>\u0000. It achieves a noise level of 27.6 ps for the number of cycles of 32. When the cycle is 1000, it achieves a maximum integral nonlinearity (INL) of 80 ps (+53 ps/-27 ps) with a resolution of 8.5 ps.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"127-130"},"PeriodicalIF":2.7,"publicationDate":"2024-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140559311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0