A 0.001-mm², 1.15–11-GHz Background Quadrature Phase and Duty-Cycle Error Corrector Using a NAND- Based Phase Detector in 28-nm CMOS

This letter introduces a background quadrature phase and duty-cycle error corrector featuring a shared NAND-based phase detector and a differential voltage-controlled delay line, which are used to determine and compensate for the phase and duty-cycle errors of the quadrature signals. In contrast to prior quadrature phase error correctors that require 50% duty-cycle inputs, the proposed corrector can minimize errors in both quadrature phase and duty-cycle with a wide operating frequency, low jitter, and low power consumption. Implemented in 28-nm CMOS, the prototype operates over a frequency range of 1.15–11 GHz and achieves a quadrature phase error of less than 2.3° and a duty-cycle error of less than 0.8% for input phase error up to 80°. It consumes 2.1 mW and achieves a low RMS jitter of 21.6 fs at 5 GHz while occupying only 0.001 mm2.