A 2048×60m4 SRAM Design in Intel 4 With Around-the-Array Power Delivery Scheme Using PowerVia

IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Solid-State Circuits Letters Pub Date : 2024-08-14 DOI:10.1109/LSSC.2024.3443757

Daeyeon Kim;Yusung Kim;Gyusung Park;Anandkumar Mahadevan Pillai;Kunal Bannore;Tri Doan;Muktadir Rahman;Gwanghyeon Baek;Xiaofei Wang;Zheng Guo;Eric Karl

引用次数: 0

Abstract

$2048\times 60$

m4 SRAM design in Intel 4 using PowerVia is presented. Instead of integrating PowerVia directly into bitcell, an around-the-array power-delivery scheme is introduced to limit the area increase of an SRAM bitcell array, while utilizing the benefits of PowerVias in logic peripheral circuits. The measured test chip demonstrates an improved or comparable

$\rm V_{MIN}$

and performance compared to similar nonPowerVia designs. An 8.3-Mb macro comprising of HCC bitcell-based

$2048\times 60$

m4 instance is 2% smaller than similar nonPowerVia design and shows a clean voltage-frequency Shmoo.

查看原文本刊更多论文

使用 PowerVia 的英特尔 4 2048×60m4 SRAM 设计与环绕阵列供电方案

本文介绍了一种使用 PowerVia 的英特尔 4 60 美元 m4 SRAM 设计。该设计没有将 PowerVia 直接集成到位元组中，而是引入了一种环绕阵列的功率传输方案，以限制 SRAM 位元组面积的增加，同时在逻辑外围电路中利用 PowerVias 的优势。与类似的非 PowerVia 设计相比，测量的测试芯片在 $\rm V_{MIN}$ 和性能方面均有改进或相当。一个由基于 HCC 位元组的 $2048/times 60$ m4 实例组成的 8.3-Mb 宏比类似的非 PowerVia 设计小 2%，并显示出干净的电压-频率 Shmoo。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

IEEE Solid-State Circuits Letters Engineering-Electrical and Electronic Engineering

CiteScore

4.30

自引率

3.70%

发文量