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IEEE Solid-State Circuits Letters最新文献

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A 1.59 pJ/b 112-Gb/s PAM-4 and 1.06 pJ/b 168-Gb/s PAM-8 Resistor-Less 7-bit SST DAC-Based Transmitter With 8-Tap FFE 1.59 pJ/b 112-Gb/s PAM-4和1.06 pJ/b 168-Gb/s PAM-8无电阻7位SST dac发射机
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-08-10 DOI: 10.1109/LSSC.2026.3722281
Yao-Hung Tsai;Ming-Han Chuang;Shen-Iuan Liu
{"title":"A 1.59 pJ/b 112-Gb/s PAM-4 and 1.06 pJ/b 168-Gb/s PAM-8 Resistor-Less 7-bit SST DAC-Based Transmitter With 8-Tap FFE","authors":"Yao-Hung Tsai;Ming-Han Chuang;Shen-Iuan Liu","doi":"10.1109/LSSC.2026.3722281","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3722281","url":null,"abstract":"A resistor-less 7-bit source-series-termination (SST) digital-to-analog converter (DAC)-based transmitter (TX) with an 8-tap feedforward equalizer (FFE) is presented. Three different resistor-less SST segments (SSTSs) are employed to achieve low capacitance, compact area, and scaling friendliness. To reduce the output jitter of the 4:1 multiplexer due to the inter-symbol-interference (ISI), the dual-feedback equalizer (DFEQ) is proposed. This TX is fabricated in 28-nm CMOS and has a maximum output swing of <inline-formula> <tex-math>$1.1~V_{mathrm {ppd}}$ </tex-math></inline-formula>. For the 112-Gb/s pulse-amplitude-modulation (PAM)-4 and 168-Gb/s PAM-8 data, the calculated energy efficiency is 1.59 and 1.06 pJ/b, respectively.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"226-229"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148780936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 256-Element Slepian Beamforming Accelerator With Analog Compute-In-Memory Multiplication and Accumulation 具有模拟内存中计算乘法和积累的256元睡眠波束形成加速器
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-03-05 DOI: 10.1109/LSSC.2026.3690381
Wei-Chun Wang;Shida Zhang;Coleman DeLude;Laith Shamieh;Nael Mizanur Rahman;Isha Chakraborty;Justin Romberg;Saibal Mukhopadhyay
{"title":"A 256-Element Slepian Beamforming Accelerator With Analog Compute-In-Memory Multiplication and Accumulation","authors":"Wei-Chun Wang;Shida Zhang;Coleman DeLude;Laith Shamieh;Nael Mizanur Rahman;Isha Chakraborty;Justin Romberg;Saibal Mukhopadhyay","doi":"10.1109/LSSC.2026.3690381","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3690381","url":null,"abstract":"An analog compute-in-memory (CIM) Slepian beamforming (SBF) accelerator is introduced for large-scale multi-input–multi-output (MIMO). The design performs complex-valued vector–matrix multiplication in the analog domain to project 256 I/Q inputs into a low-dimensional Slepian subspace and uses a digital backend with 4-tap FIR filters to generate one output beam. A test chip fabricated in 28-nm CMOS demonstrates a 20.5-dB peak-to-sidelobe ratio (PSLR) over a 280-MHz bandwidth while consuming 414 mW.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"154-157"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148003525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 60-GHz Class- F2,3 Standing-Wave Oscillator Employing Triple-Line Resonator Achieving −189-dBc/Hz FoM in 65-nm CMOS 采用三线谐振器的60ghz f23,3驻波振荡器在65nm CMOS中实现- 189 dbc /Hz的FoM
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-03-13 DOI: 10.1109/LSSC.2026.3693153
Wei-Yu Lin;Nikhil Jain;Jun-Chau Chien
{"title":"A 60-GHz Class- F2,3 Standing-Wave Oscillator Employing Triple-Line Resonator Achieving −189-dBc/Hz FoM in 65-nm CMOS","authors":"Wei-Yu Lin;Nikhil Jain;Jun-Chau Chien","doi":"10.1109/LSSC.2026.3693153","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3693153","url":null,"abstract":"Implementing oscillators with harmonic engineering beyond 60-GHz poses significant challenges due to the need for small inductors resonating beyond 120 GHz. To address this issue, this work presents a 60-GHz standing-wave oscillator (SWO) with both second- and third-harmonic boosting for phase noise reduction. A triple-line resonator is proposed to sustain both fundamental and second-harmonic resonance. The measurement results of the class-<inline-formula> <tex-math>$mathrm {F}_{2,3}$ </tex-math></inline-formula> SWO in TSMC 65-nm LP technology achieve −101.1 dBc/Hz at 1-MHz offset while consuming 5.5 mW with an FoM of −189 dBc/Hz.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"158-161"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148003640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 4-GS/s 53.5-dB SNDR 12.9 fJ/conv. TI-SAR ADC With Capacitive Nonlinearity Compensation and Dual-Mode Offset Calibration 4-GS/s 53.5 db SNDR 12.9 fJ/conv。带电容非线性补偿和双模偏移校准的TI-SAR ADC
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-07-14 DOI: 10.1109/LSSC.2026.3713349
Jiazhen Ni;Dayi Zhou;Minqing Cai;Chen Chen;Xiang Gao;Seung-Chul Lee
{"title":"A 4-GS/s 53.5-dB SNDR 12.9 fJ/conv. TI-SAR ADC With Capacitive Nonlinearity Compensation and Dual-Mode Offset Calibration","authors":"Jiazhen Ni;Dayi Zhou;Minqing Cai;Chen Chen;Xiang Gao;Seung-Chul Lee","doi":"10.1109/LSSC.2026.3713349","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3713349","url":null,"abstract":"Successive approximation register (SAR) analog-to-digital converters (ADCs) often employ dual-mode dynamic comparators to achieve both high speed and low noise. However, under low-supply operation, offset drift from mode transitions and degraded front-end linearity due to limited signal headroom become critical challenges. To address these issues, an adaptive current-injection scheme suppresses the dynamic offset between coarse and fine decisions. Additionally, a sampling-phase pull-up drives the comparator input pair into cutoff, shaping the input capacitance and extending the linear input range. Implemented in a 12-nm FinFET process, the proposed comparator is integrated into an 11-bit, 4-GS/s, 8-way time-interleaved (TI) SAR ADC. The prototype occupies 0.12 mm2 and consumes 20 mW from a 1.2-V supply. Measurement results show a Nyquist signal-to-noise-and-distortion ratio (SNDR) of 53.5 dB and a spurious-free dynamic range (SFDR) of 70.1 dBc, corresponding to a Walden Figure-of-Merit (FoM) of 12.9 fJ/conversion-step.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"214-217"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148747404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 42-Gb/s PAM-3 Transmitter With a CML Driver and a Dual-Mode Encoder for Process-Variation-Tolerant Middle-Level Generation 一个42gb /s的PAM-3发射机，带有CML驱动程序和双模编码器，用于容忍过程变化的中间层生成
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-08-04 DOI: 10.1109/LSSC.2026.3720204
Seungwoo Park;Taehwan Kim;Changmin Sim;Seongcheol Kim;Junseob So;Hwaseok Shin;Seon-Been Lee;Chulwoo Kim
{"title":"A 42-Gb/s PAM-3 Transmitter With a CML Driver and a Dual-Mode Encoder for Process-Variation-Tolerant Middle-Level Generation","authors":"Seungwoo Park;Taehwan Kim;Changmin Sim;Seongcheol Kim;Junseob So;Hwaseok Shin;Seon-Been Lee;Chulwoo Kim","doi":"10.1109/LSSC.2026.3720204","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3720204","url":null,"abstract":"This letter presents a 42-Gb/s differential pulse-amplitude modulation (PAM-3) transmitter using a current-mode logic (CML) driver and a dual-mode 3B2T encoder for process-variation-tolerant middle-level (M-level) generation. The encoder selects between two M-level encoding schemes to compensate for load-resistor and driver-current-path mismatches with minimal logic overhead, reducing the standard deviation of the M-level offset by 40% in 1000-run Monte Carlo simulations. Fabricated in 28-nm CMOS, the prototype occupies 0.015 mm2 and consumes 66.3 mW at 42 Gb/s, achieving 1.58 pJ/b. Measurements verify M-level offset compensation under mismatch emulation and improved eye openings with a 3-tap feed-forward equalizer (FFE).","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"234-237"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148836947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Practical MRAM Logic-in-Memory Platform With Reference-Bitline Structure 一种实用的参考位线结构MRAM内存逻辑平台
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-08-31 DOI: 10.1109/LSSC.2026.3729230
Seongmin Ahn;Minjun Jang;Mingu Han;Bayartulga Ishdorj;Siyeol Lee;Taehui Na
{"title":"A Practical MRAM Logic-in-Memory Platform With Reference-Bitline Structure","authors":"Seongmin Ahn;Minjun Jang;Mingu Han;Bayartulga Ishdorj;Siyeol Lee;Taehui Na","doi":"10.1109/LSSC.2026.3729230","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3729230","url":null,"abstract":"The memory wall due to data movement is a major challenge that limits performance and energy efficiency in bitwise-operation-intensive applications. To address this issue, this article proposes a global merged reference-based magnetic random access memory (MRAM) logic-in-memory (LIM) structure. The proposed structure generates operation-specific reference resistances by controlling the effective parallelism of the reference bitlines (Ref-BLs) while maintaining the initial reference-cell configuration, thereby supporting memory read and two-input <sc>and</small>/<sc>or</small> operations without rewriting the reference cells or using dedicated <sc>and</small>/<sc>or</small> logic blocks. A read-disturbance-free (RDF) scheme is also applied to protect the frequently accessed reference cells. A 32-kb test chip fabricated in a 28-nm FD-SOI process achieved sensing yields of 100%, 98.63%, and 99.73% and normalized energies per bit of <inline-formula> <tex-math>$0.97times $ </tex-math></inline-formula>, <inline-formula> <tex-math>$0.54times $ </tex-math></inline-formula>, and <inline-formula> <tex-math>$0.49times $ </tex-math></inline-formula> relative to conventional MRAM for memory read, <sc>or</small>, and <sc>and</small> operations, respectively. Full-system evaluations achieved speedups of <inline-formula> <tex-math>$2.23times $ </tex-math></inline-formula>–<inline-formula> <tex-math>$2.50times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$3.14times $ </tex-math></inline-formula>–<inline-formula> <tex-math>$4.97times $ </tex-math></inline-formula>, with normalized dynamic energy consumption of <inline-formula> <tex-math>$0.39times $ </tex-math></inline-formula>–<inline-formula> <tex-math>$0.44times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$0.23times $ </tex-math></inline-formula>–<inline-formula> <tex-math>$0.30times $ </tex-math></inline-formula>, for bitmap-index queries and bitmap-based breadth-first search (BFS), respectively.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"266-269"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148985949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An 18.4-Gb/s/pin Simultaneous Bidirectional Transceiver for Post HBM4 Using Four-Phase Hybrid Timing Alignment and Dual Equalization 基于四相混合时序对准和双均衡的HBM4后置18.4 gb /s/引脚同步双向收发器
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-03-22 DOI: 10.1109/LSSC.2026.3696268
Minchang Kim;Hankyu Chi;Sooncheol Kwon;Icsu Oh;Seulgi Kim;Heewoong Song;Daeho Yun;Jaehong Jeong;Daejoon Kim;Kichul Hong;Jeonghyun Park;Woo-Seok Choi;Hae-Kang Jung;Hoyoung Son;Inchul Jeong;Hyungsoo Kim;Jonghwan Kim
{"title":"An 18.4-Gb/s/pin Simultaneous Bidirectional Transceiver for Post HBM4 Using Four-Phase Hybrid Timing Alignment and Dual Equalization","authors":"Minchang Kim;Hankyu Chi;Sooncheol Kwon;Icsu Oh;Seulgi Kim;Heewoong Song;Daeho Yun;Jaehong Jeong;Daejoon Kim;Kichul Hong;Jeonghyun Park;Woo-Seok Choi;Hae-Kang Jung;Hoyoung Son;Inchul Jeong;Hyungsoo Kim;Jonghwan Kim","doi":"10.1109/LSSC.2026.3696268","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3696268","url":null,"abstract":"This letter presents a simultaneous bidirectional (SBD) transceiver for post HBM4. It is difficult to increase the data rate due to poor channel characteristics of the silicon interposer and the limited physical area of the IO in high-bandwidth memory (HBM) interface. SBD signaling is attractive because it doubles the per-pin bandwidth without increasing the data rate. The SBD transceiver was demonstrated using four-phase hybrid timing alignment and dual equalization. The bidirectional signals are aligned on both sides through CH reach optimization at the target frequency. This simplifies the bidirectional signals on both sides and reduces echo effects. The hybrid scheme using four-phase clocking mitigates RX margin reduction due to TX replica mismatch. In addition, a dual equalization scheme is proposed to compensate for the bidirectional ISI of the SBD signal. The prototype transceiver is implemented using RDL fan-out wafer-level package (FOWLP) and fabricated in a 1b-nm DRAM process with 70-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m bump pitch, such as HBM4. The transceiver supports the SBD operation up to 18.4 Gb/s/pin on 6-mm traces, similar in length to the HBM4 system. The transceiver achieves the highest per-pin bandwidth compared to previous works.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"182-185"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148236330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Low-Power MRAM-Based Nonvolatile Flip-Flop Architecture for Register and System Applications 一种低功耗基于mram的非易失性触发器架构，用于寄存器和系统应用
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-07-14 DOI: 10.1109/LSSC.2026.3713204
Bayartulga Ishdorj;Taehui Na
{"title":"A Low-Power MRAM-Based Nonvolatile Flip-Flop Architecture for Register and System Applications","authors":"Bayartulga Ishdorj;Taehui Na","doi":"10.1109/LSSC.2026.3713204","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3713204","url":null,"abstract":"This work presents a minimal nonvolatile flip-flop (NVFF) hybrid architecture and an NV static contention-free differential FF (nvSCDFF) cell that reduces the overhead associated with replicated NV circuitry in conventional in situ NVFFs while enabling low power. By using only one NVFF per column and compact SCDFF-based volatile flip-flops (FFs), the design removes per-cell write drivers and sense amplifiers, reducing area, power, and energy. A symmetric self-referenced sensing achieves the required <inline-formula> <tex-math>$4sigma $ </tex-math></inline-formula> restore yield without assist circuitry. Monte Carlo simulations and a 28-nm test chip demonstrate robust restore operation and low-voltage functionality.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"206-209"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148627284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 64-Gb/s/pin 0.25-pJ/b Single-Ended Short-Reach PAM4 Transceiver in 28-nm CMOS 64gb /s/引脚0.25 pj /b单端短达PAM4收发器
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-08-07 DOI: 10.1109/LSSC.2026.3721808
Kshitiz Tyagi;Kunbo Ma;Joung Won Park;Behzad Razavi
{"title":"A 64-Gb/s/pin 0.25-pJ/b Single-Ended Short-Reach PAM4 Transceiver in 28-nm CMOS","authors":"Kshitiz Tyagi;Kunbo Ma;Joung Won Park;Behzad Razavi","doi":"10.1109/LSSC.2026.3721808","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3721808","url":null,"abstract":"We present a transceiver architecture for single-ended PAM4 signaling, introducing an inverter-based active-inductor-terminated front end that obviates the need for further equalizer stages, substantially reducing power and area. Realized in 28-nm CMOS technology, the four-lane link operates at 64 Gb/s/pin with a bit error rate (BER) less than <inline-formula> <tex-math>$10{^{-12}}$ </tex-math></inline-formula> while consuming only 0.25 pJ/b (0.2 pJ/b at 50 Gb/s) from a 1-V supply and achieves bandwidth density greater than 28 Tb/s/mm2.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"230-233"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148836943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Low-Power 10 Mbps Squaring-First UWB Receiver Using Frequency Hopping and Two-Tone Modulation 采用跳频和双音调制的低功耗10mbps平方优先UWB接收机
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-07-24 DOI: 10.1109/LSSC.2026.3716852
Lexie Drackley;Aman Gupta;David D. Wentzloff
{"title":"A Low-Power 10 Mbps Squaring-First UWB Receiver Using Frequency Hopping and Two-Tone Modulation","authors":"Lexie Drackley;Aman Gupta;David D. Wentzloff","doi":"10.1109/LSSC.2026.3716852","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3716852","url":null,"abstract":"This article presents a low-power 10 Mbps squaring-first ultrawideband (UWB) receiver using frequency hopping (FH) code-division multiple-access (FH-CDMA) and two-tone OOK modulation for wireless personal area networks (WPANs). The two-tone receiver architecture preserves IF filtering, improves resilience to narrowband interference (NBI), and saves power by eliminating the RF local oscillator (LO). FH is applied to both two-tone spacing and center frequency, where spacing-FH enables multiple-access communication, while center-FH distributes signal energy across the UWB spectrum and improves NBI tolerance. Implemented in 65 nm CMOS, the receiver achieves −71.4 dBm sensitivity at 10 Mbps while consuming <inline-formula> <tex-math>$987~mu $ </tex-math></inline-formula>W, demonstrating improved tolerance to a 6 GHz blocker and 1 dB sensitivity degradation under two-user reception.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"262-265"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148985822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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