IEEE Solid-State Circuits Letters最新文献_第5页

An 18-nW CMOS Current and Voltage Reference Circuit With Low Line Sensitivity and Wide Temperature Range 具有低线路灵敏度和宽温度范围的 18-nW CMOS 电流和电压基准电路

IF 2.2

IEEE Solid-State Circuits Letters Pub Date : 2024-03-30 DOI: 10.1109/LSSC.2024.3407583

I-Fan Lin;Yu-Chu Tsai;Heng-Li Lin;Yu-Te Liao

{"title":"An 18-nW CMOS Current and Voltage Reference Circuit With Low Line Sensitivity and Wide Temperature Range","authors":"I-Fan Lin;Yu-Chu Tsai;Heng-Li Lin;Yu-Te Liao","doi":"10.1109/LSSC.2024.3407583","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3407583","url":null,"abstract":"This letter presents a design for a voltage and current reference (VCR) that utilizes a 0.18-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m CMOS process. The design employs stacked-diode MOS transistors (SDMTs) to generate a voltage that is complementary to absolute temperature for the current reference (CR). By adjusting the transistor size ratio, this bias voltage exhibits the similar temperature coefficient (TC) as that of the resistor in the CR. To enhance temperature compensation, a reversely biased transistor is employed in the voltage reference (VR). Additionally, the cascode current mirror and SDMTs in the VR mitigate supply sensitivity in both voltage and current outputs. The VCR achieves a TC of 124 ppm/°C in VR and 264 ppm/°C in CR over a temperature range of \u0000<inline-formula> <tex-math>$- 40~^{circ }$ </tex-math></inline-formula>\u0000C to \u0000<inline-formula> <tex-math>$130~^{circ }$ </tex-math></inline-formula>\u0000C. Furthermore, it achieves a line sensitivity of 0.011 %/V in VR and 0.094 %/V in CR while operating at 18.51 nW at room temperature. The active chip area of the VCR is approximately \u0000<inline-formula> <tex-math>$25~000~mu $ </tex-math></inline-formula>\u0000m2.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141474867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 23.9-μW 13.6-Bit Period Modulation-Based Capacitance-to-Digital Converter With Dynamic Current Mirror Front-End 带动态电流镜前端的 23.9μW 13.6 位基于周期调制的电容数字转换器

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-03-28 DOI: 10.1109/LSSC.2024.3382813

Hyeyeon Lee;Donguk Seo;Young-Jin Woo;Yoonmyung Lee;Inhee Lee;Youngcheol Chae

{"title":"A 23.9-μW 13.6-Bit Period Modulation-Based Capacitance-to-Digital Converter With Dynamic Current Mirror Front-End","authors":"Hyeyeon Lee;Donguk Seo;Young-Jin Woo;Yoonmyung Lee;Inhee Lee;Youngcheol Chae","doi":"10.1109/LSSC.2024.3382813","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3382813","url":null,"abstract":"This letter proposes a low-power high-precision capacitance-to-digital converter (CDC) utilizing a dynamic current mirror (DCM) to transform a sensor input capacitance \u0000<inline-formula> <tex-math>$(C_{mathrm{ IN}})$ </tex-math></inline-formula>\u0000 into an output current. The resulting current is directly proportional to the ratio of \u0000<inline-formula> <tex-math>$C_{mathrm{ IN}}$ </tex-math></inline-formula>\u0000 to an internal reference capacitor \u0000<inline-formula> <tex-math>$(C_{mathrm {REF}})$ </tex-math></inline-formula>\u0000 and subsequently converted into a period-modulated output, facilitating simple digitization by a digital counter. The CDC achieves an extensive \u0000<inline-formula> <tex-math>$C_{mathrm{ IN}}$ </tex-math></inline-formula>\u0000 range of 1 to 68 pF without the need for a power-hungry reference buffer. Fabricated in a 65-nm CMOS process, the prototype IC occupies a small area of 0.05-mm2 and consumes only \u0000<inline-formula> <tex-math>$23.9~mu text{W}$ </tex-math></inline-formula>\u0000 even with a \u0000<inline-formula> <tex-math>$C_{mathrm{ IN}}$ </tex-math></inline-formula>\u0000 of 47 pF. It achieves a capacitance resolution of 1.65 fF for a \u0000<inline-formula> <tex-math>$C_{mathrm{ IN}}$ </tex-math></inline-formula>\u0000 of 1 pF with a conversion time of 4 ms, corresponding to a 13.6-bit effective number of bit.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140606068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Compact Phase-Domain Delta–Sigma Time-to-Digital Converter With 8.5-ps Resolution for LiDAR Applications 用于激光雷达应用的 8.5 ps 分辨率紧凑型相位域三角积分时数字转换器

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-03-27 DOI: 10.1109/LSSC.2024.3382594

Yoondeok Na;Myung-Jae Lee;Youngcheol Chae

{"title":"A Compact Phase-Domain Delta–Sigma Time-to-Digital Converter With 8.5-ps Resolution for LiDAR Applications","authors":"Yoondeok Na;Myung-Jae Lee;Youngcheol Chae","doi":"10.1109/LSSC.2024.3382594","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3382594","url":null,"abstract":"This letter introduces a compact, high-resolution time-to-digital converter (TDC) for lidar applications. In contrast to a conventional histogram-based peak detection method, this letter proposes a mean detection method using a highly digitized phase-domain delta–sigma (PD\u0000<inline-formula> <tex-math>$Delta Sigma$ </tex-math></inline-formula>\u0000) TDC. The proposed TDC operates in an incremental \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000 manner for a compact implementation and utilizing a digital integrator as a loop filter that facilitates an extended counting, resulting in significantly improved resolution. By utilizing a dual gated-ring oscillator (GRO) structure, time-quantization noise due to a residue phase of GRO is effectively mitigated. To address the issue of single-photon avalanche diode (SPAD) signals due to their stochastic nature, a dual time window is proposed to compensate for counting error when SPAD trigger missing occurs. Fabricated in a 65-nm CMOS process, the prototype TDC occupies only an area of \u0000<inline-formula> <tex-math>$2000~mu text{m}~^{mathrm{ 2}}$ </tex-math></inline-formula>\u0000. It achieves a noise level of 27.6 ps for the number of cycles of 32. When the cycle is 1000, it achieves a maximum integral nonlinearity (INL) of 80 ps (+53 ps/-27 ps) with a resolution of 8.5 ps.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140559311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 50–67-GHz Transformer-Based Six-Port Balanced-to-Unbalanced Quadrature Hybrid Coupler 基于变压器的 50-67-GHz 六端口平衡至不平衡正交混合耦合器

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-03-26 DOI: 10.1109/LSSC.2024.3381811

Yang Gao;Howard C. Luong

引用次数: 0

Corrections to “A Dynamic Power-Only Compute-in-Memory Macro With Power-of-Two Nonlinear SAR ADC for Nonvolatile Ferroelectric Capacitive Crossbar Array” 对 "用于非易失性铁电电容式交叉排列的动态只需电源的内存计算宏与两功率非线性 SAR ADC "的更正

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-03-21 DOI: 10.1109/LSSC.2024.3371728

Injune Yeo;Wangxin He;Yuan-Chun Luo;Shimeng Yu;Jae-Sun Seo

引用次数: 0

A 4-Element Ka-Band Phased-Array Receiver With Code-Domain Hybrid Beamforming 具有码域混合波束成形功能的 4 元 Ka 波段相控阵接收器

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-03-20 DOI: 10.1109/LSSC.2024.3379562

Ziyi Lin;Haikun Jia;Chuanming Zhu;Wei Deng;Huabing Liao;Bao Shi;Lujie Hao;Xiangrong Huang;Baoyong Chi

引用次数: 0

A Wideband Low-Noise Linear LiDAR Analog Front-End Achieving 1.6-GHz Bandwidth, 2.7-pA/Hz0.5 Input-Referred Noise, and 103-dBΩ Transimpedance Gain 宽带低噪声线性激光雷达模拟前端，实现 1.6 GHz 带宽、2.7-pA/Hz0.5 输入参考噪声和 103-dBΩ 跨阻增益

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-03-19 DOI: 10.1109/LSSC.2024.3378093

Zhao Zhang;Yidan Zhang;Yiqing Xu;Xinyu Shen;Guike Li;Nan Qi;Jian Liu;Nanjian Wu;Liyuan Liu

引用次数: 0

A 6.4-Gb/s/pin nand Flash Memory Multichip Package Employing a Frequency Multiplying Bridge Chip for Scalable Performance and Capacity Storage Systems 采用倍频桥接芯片的 6.4 GB/s/针 nand 闪存多芯片封装，用于可扩展性能和容量的存储系统

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-03-14 DOI: 10.1109/LSSC.2024.3377263

Shinichi Ikeda;Akira Iwata;Goichi Otomo;Tomoaki Suzuki;Hiroaki Iijima;Mikio Shiraishi;Shinya Kawakami;Masatomo Eimitsu;Yoshiki Matsuoka;Kiyohito Sato;Shigehiro Tsuchiya;Yoshinori Shigeta;Takuma Aoyama

{"title":"A 6.4-Gb/s/pin nand Flash Memory Multichip Package Employing a Frequency Multiplying Bridge Chip for Scalable Performance and Capacity Storage Systems","authors":"Shinichi Ikeda;Akira Iwata;Goichi Otomo;Tomoaki Suzuki;Hiroaki Iijima;Mikio Shiraishi;Shinya Kawakami;Masatomo Eimitsu;Yoshiki Matsuoka;Kiyohito Sato;Shigehiro Tsuchiya;Yoshinori Shigeta;Takuma Aoyama","doi":"10.1109/LSSC.2024.3377263","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3377263","url":null,"abstract":"This letter describes a NAND flash memory multichip package (NAND MCP) incorporating a developed LSI interface (IF) Chip (Bridge Chip) in which the IF to and from the solid-state drive (SSD) controller has twice the speed as that of the IF to and from the NAND dies even with multiple packages on each printed circuit board (PCB) channel. This NAND MCP allows to reduce the number of NAND IF channels on the PCB while retaining the total bandwidth of the SSD and increasing the capacity. The Bridge Chip employs a 2:1 frequency multiplying function to bridge the speed gap, a fast-lock phase-locked loop (PLL) with an extended pull-in range and 16-cycle lock time to enhance the IF performance with its input-jitter filtering effect, and equalizers to compensate for intersymbol interference and reflected noise in up to a 4-drop configuration. The Bridge Chip implemented in a 12-nm CMOS process is demonstrated at 6.4 Gb/s/pin with 2.85-pJ/b I/O energy efficiency in a read operation. The NAND MCP incorporating the Bridge Chip and eight 1-Tb NAND dies achieves data transmission to and from field-programmable gate array (FPGA) at twice the speed of the NAND IF in a 2-drop configuration.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140348399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Multichannel Injection-Locked OOK Transmitter With Current Mode Edge-Combining Power Amplifier 带电流模式边缘合成功率放大器的多通道注入锁定 OOK 发射机

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-03-11 DOI: 10.1109/LSSC.2024.3375329

Sheng-Kai Chang;Zhi-Wei Lin;Kuang-Wei Cheng

{"title":"A Multichannel Injection-Locked OOK Transmitter With Current Mode Edge-Combining Power Amplifier","authors":"Sheng-Kai Chang;Zhi-Wei Lin;Kuang-Wei Cheng","doi":"10.1109/LSSC.2024.3375329","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3375329","url":null,"abstract":"This letter introduces an ultralow-power ON–OFF keying (OOK) wireless transmitter incorporating innovative multiphase injection locking and frequency multiplication techniques. The transmitter leverages a current mode class-D edge-combining power amplifier, ensuring high-energy efficiency in frequency multiplication to generate the carrier frequency. With a primary focus on facilitating multichannel support for Internet of Things (IoT) applications, the prototype incorporates a low-frequency phase-rotation-based frequency synthesizer. To mitigate the quantization noise in \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000 modulator of the synthesizer, the design combines an N-path filter and injection-locked ring oscillators to effectively filter out the shaped far-out phase noise. The prototype, fabricated in TSMC 90-nm CMOS, achieves an output power of −6.9 dBm with a power consumption of \u0000<inline-formula> <tex-math>$890~mu text{W}$ </tex-math></inline-formula>\u0000 at a 0.75-V supply voltage. It supports data rates of up to 40 Mb/s under OOK modulation, resulting in an energy efficiency of 22 pJ/bit and a global efficiency of 23%, showcasing its effectiveness in balancing performance and power consumption.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140310160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A VCO With Robust Implicit Common-Mode Resonance Against Nonideal Decoupling Network 针对非理想去耦网络的稳健隐含共模共振 VCO

IF 2.7

IEEE Solid-State Circuits Letters Pub Date : 2024-03-10 DOI: 10.1109/LSSC.2024.3399228

Dingxin Xu;Zheng Sun;Yuang Xiong;Yuncheng Zhang;Hongye Huang;Zezheng Liu;Ashbir Aviat Fadila;Atsushi Shirane;Kenichi Okada

引用次数: 0