IEEE Solid-State Circuits Letters最新文献_第5页

A Time-Domain CNN Engine With Adaptive-Precision Computing and Threshold-Controllable Prediction for Edge Computing 一种边缘计算自适应精度计算和阈值可控预测的时域CNN引擎

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IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-04-28 DOI: 10.1109/LSSC.2026.3687395

Aoming Zhan;Ye Zhao;Yulin Zhang;Gengchen Han;Qihang Jiang;Long Chen;Yumei Zhou;Shushan Qiao

{"title":"A Time-Domain CNN Engine With Adaptive-Precision Computing and Threshold-Controllable Prediction for Edge Computing","authors":"Aoming Zhan;Ye Zhao;Yulin Zhang;Gengchen Han;Qihang Jiang;Long Chen;Yumei Zhou;Shushan Qiao","doi":"10.1109/LSSC.2026.3687395","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3687395","url":null,"abstract":"With the growing demand for energy-efficient convolutional neural network (CNN) accelerators in edge intelligence, conventional digital CNN processors with fixed precision incur excessive switching energy and limited scalability. This work presents a time-domain CNN (TD-CNN) engine that achieves adaptive precision and computation reduction for ultralow-power operation. The main features include: 1) a dual-precision mode-switching DTC (DPMS-DTC) supporting both low-power (LP) and high-linearity (HL) modes; 2) a bit-sliced hybrid-precision (BSHP) MAC computing technique that achieves high accuracy with low power consumption; and 3) a threshold-controllable near-negative prediction (TCNNP) technique aimed at reducing redundant MAC operations. Fabricated in a 55-nm CMOS process, the engine achieves 28.7–<inline-formula> <tex-math>$412.5~mu $ </tex-math></inline-formula>W power consumption and a 255.7–993.3 TOPS/W figure-of-merit. It delivers 92.10%–90.91% CIFAR-10 accuracy using 6-bit inputs and weights. With a 1% accuracy allowance, TCNNP reduces MAC operations by 59%.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"142-145"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147828914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

FeFET-Based CMOS Current Starvation Programmable Delay Element 基于fet的CMOS电流耗尽可编程延迟元件

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IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-03-11 DOI: 10.1109/LSSC.2026.3692304

Albi Mema;Simon Thomann;Hussam Amrouch

{"title":"FeFET-Based CMOS Current Starvation Programmable Delay Element","authors":"Albi Mema;Simon Thomann;Hussam Amrouch","doi":"10.1109/LSSC.2026.3692304","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3692304","url":null,"abstract":"Programmable delay elements (PDEs) are crucial circuit building blocks that enable precise timing adjustments of signal transitions. They are used in various critical applications, like time-to-digital converters. They are often used to mitigate aging by clock skew tuning postfabrication. However, typical CMOS PDE designs require many transistors while still offering a limited delay range. This work implements a PDE based on the current starvation concept and utilizes ferroelectric FETs (FeFETs) to realize delay programmability in a nonvolatile manner. We fabricated 28 nm FeFET (both n-type and p-type) and measured their characteristics. We then design, simulate, and tape-out the proposed PDE with a ring oscillator (RO) as circuit-under-test to evaluate and demonstrate our concept. The frequency of the RO is successfully controlled via the polarization of the FeFETs and was measured via a wafer probe setup. Our proposed design offers a wide range of modulation from 2.8 MHz (when the FeFETs are programmed to the high threshold voltage (<inline-formula> <tex-math>$V_{text {TH}}$ </tex-math></inline-formula>) state) up to 7.47 MHz (when the FeFETs are programmed to the low <inline-formula> <tex-math>$V_{text {TH}}$ </tex-math></inline-formula> state). This in turn corresponds to 223.27 ns difference in the period between the two ferroelectric polarization states that put the underlying transistor into two distinguished low and high resistive states.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"166-169"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11515122","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148003587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Minimizing the Noise in Low-Current Sensing by MOSFET p-n Junction Diode Feedback 利用MOSFET p-n结二极管反馈最小化低电流传感中的噪声

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IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-03-13 DOI: 10.1109/LSSC.2026.3692971

Ehsan Semsar Parapari;Marco Bennati;Michele Biondi;Marco Crescentini;Federico Thei

{"title":"Minimizing the Noise in Low-Current Sensing by MOSFET p-n Junction Diode Feedback","authors":"Ehsan Semsar Parapari;Marco Bennati;Michele Biondi;Marco Crescentini;Federico Thei","doi":"10.1109/LSSC.2026.3692971","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3692971","url":null,"abstract":"This letter proposes a transimpedance amplifier (TIA) architecture that minimizes noise for continuous-time (CT) low-current sensing. The approach leverages a MOSFET to realize a pure p-n junction diode as the TIA feedback element, such that MOS channel conduction is completely suppressed. Therefore, channel-induced noise contributions associated with conventional MOS-based feedback TIAs are mitigated, and the input-referred noise is dominated by shot noise due to intrinsic p-n junction mechanisms, which remains ultralow at pA-level input currents. To enable proper evaluation, the proposed concept is combined with architectural enhancements, ensuring symmetric and linear operation. The implemented TIA prototype, fabricated in a 0.35-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS process, demonstrates a minimum input-referred current noise density of 1.5 fA/<inline-formula> <tex-math>$sqrt {text {Hz}}$ </tex-math></inline-formula>, while providing a transimpedance gain of 100 M<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula> with a–3 dB bandwidth of 700 kHz.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"162-165"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148003590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Reconfigurable Multimode Readout IC for Nonconductive and Capacitive Sensing With 33.9-dB SNR on 6.5-in AMOLED Panels 一种用于6.5英寸AMOLED面板上信噪比为33.9 db的非导电和电容式传感的可重构多模读出IC

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IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-04-02 DOI: 10.1109/LSSC.2026.3680164

Sang Weun Kim;Jun Seong Kim;Dabin Yun;Seunghoon Ko

引用次数: 0

A Sensing-Security Co-Design Based on Intrinsic Device Variations for Self-Authenticating Sensors 基于自认证传感器内在器件变化的传感-安全协同设计

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IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-08-20 DOI: 10.1109/LSSC.2026.3725256

Ruochen Wang;Tetsuya Hirose;Jun Shiomi;Yoshihiro Midoh;Takuji Miki;Makoto Nagata;Noriyuki Miura

引用次数: 0

1–1.7-GHz Single-Voltage-Controlled Tunable MMIC BPF With Over 45-dB Rejection to 30 GHz Using Tapped Inductor Technique 采用抽头电感技术的1 - 1.7 GHz单电压控制可调谐MMIC BPF，抑制超过45 db至30 GHz

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IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-02-26 DOI: 10.1109/LSSC.2026.3668386

Di Lu;Menghan Sun;Baoqi Zhu;Xin Jiang;Ming Yu

引用次数: 0

A 12 b 180-MS/s Pipelined-SAR ADC With a Low-Power Calibration-Free RA and Hardware-Efficient SAR Logic 具有低功耗免校准RA和硬件高效SAR逻辑的12b 180 ms /s流水线SAR ADC

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IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-03-26 DOI: 10.1109/LSSC.2026.3697220

Guo Wei;Rui Zhang;Fule Li;Hanjun Jiang;Zhihua Wang

引用次数: 0

miniSQI: A Compact and Low-Power SQIsign-1D Post-Quantum Digital Signature Verification Accelerator 微型低功耗SQIsign-1D后量子数字签名验证加速器

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IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-08-06 DOI: 10.1109/LSSC.2026.3720807

Krishna Sai Tarun Ramapragada;Utsav Banerjee

引用次数: 0

A Multiband Ultralow-Power Transceiver With Two-Step Wake-Up Reception 具有两步唤醒接收的多波段超低功耗收发器

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IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-04-08 DOI: 10.1109/LSSC.2026.3681917

Thinh Tran-Dinh;Hafiz Usman Mahmood;Jinglong Xu;Keun-Mok Kim;Kyung-Sik Choi;Jaeheon Lee;Jinho Ko;Sang-Gug Lee;Jusung Kim

引用次数: 0

Merged-Reference-Compatible Offset-Canceling Discharge-Based Sensing Circuit for STT-MRAM in 28-nm CMOS 基于合并参考兼容偏移抵消放电的28纳米CMOS STT-MRAM传感电路

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IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-07-20 DOI: 10.1109/LSSC.2026.3715234

Jaeyong Jang;Mingu Han;Jaehwan Kim;Taehui Na

{"title":"Merged-Reference-Compatible Offset-Canceling Discharge-Based Sensing Circuit for STT-MRAM in 28-nm CMOS","authors":"Jaeyong Jang;Mingu Han;Jaehwan Kim;Taehui Na","doi":"10.1109/LSSC.2026.3715234","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3715234","url":null,"abstract":"This article proposes an offset-canceling (OC) discharge-based sensing circuit (OCDC) for spin-transfer-torque magnetic random access memory (STT-MRAM). The proposed circuit simultaneously implements a merged reference line (MRL) architecture and threshold voltage (<inline-formula> <tex-math>$mathbf {V}_{mathbf {TH}}$ </tex-math></inline-formula>) mismatch cancellation, resolving the structural incompatibility between the conventional OC schemes and MRL. A diode-connection-based, self-biasing mechanism further eliminates the need for an external clamp voltage generator, providing robustness against process-voltage-temperature (PVT) variations. A 30 720-bit test chip fabricated in a 28-nm FD-SOI process demonstrates that at <inline-formula> <tex-math>$mathbf {V}_{mathbf {DD}} =0.8$ </tex-math></inline-formula> V and <inline-formula> <tex-math>$mathbf {t}_{mathbf {sen}} = 2$ </tex-math></inline-formula> ns, the OCDC reduces the fail bit count (FBC) from 2007 to 0 for Read 0 and from 3957 to 0 for Read 1 compared to the conventional sensing circuit. The robustness of the proposed circuit is further validated through Monte Carlo simulations over a temperature range from −45°C to 90°C and a magnetic tunnel junction (MTJ) resistance variation ranging from 6% to 15%.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"210-213"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148747167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0