Kedar Bhatt;Stafford Hutchins;Atresh Sanne;Mohammad M. Hasan;Zhanping Chen;Jaydeep P. Kulkarni
{"title":"基于Intel 4逻辑技术的快速响应、低Vmin的带隙二极管电压检测电路","authors":"Kedar Bhatt;Stafford Hutchins;Atresh Sanne;Mohammad M. Hasan;Zhanping Chen;Jaydeep P. Kulkarni","doi":"10.1109/LSSC.2025.3572385","DOIUrl":null,"url":null,"abstract":"A fast, accurate, single-rail voltage detection circuit (VDC) is presented. Low voltage operation is achieved by a variable gain Charge Pump (CP) followed by a Low-Dropout regulator (LDO). An Open-loop band gap reference (BGREF), passed to a dynamic comparator, achieves an undervoltage trip point of 0.62 V with 8.7 mV sigma, and an overvoltage trip point of 1.22 V with 12 mV sigma, demonstrated on Intel 4 silicon prototype. The design operates without any filter cap, allowing a fast, power-on ramp of <inline-formula> <tex-math>$2~\\mu $ </tex-math></inline-formula>s, and brown-out detection of <200 ns. A voltage band detection of 0.48–1.22 V is enabled through a finite-state machine (FSM) to modify CP and LDO gain depending on input voltage.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"157-160"},"PeriodicalIF":2.0000,"publicationDate":"2025-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Bandgap Diode-Based Voltage Band Detection Circuit With Fast Response Time and Low Vmin on Intel 4 Logic Technology\",\"authors\":\"Kedar Bhatt;Stafford Hutchins;Atresh Sanne;Mohammad M. Hasan;Zhanping Chen;Jaydeep P. Kulkarni\",\"doi\":\"10.1109/LSSC.2025.3572385\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A fast, accurate, single-rail voltage detection circuit (VDC) is presented. Low voltage operation is achieved by a variable gain Charge Pump (CP) followed by a Low-Dropout regulator (LDO). An Open-loop band gap reference (BGREF), passed to a dynamic comparator, achieves an undervoltage trip point of 0.62 V with 8.7 mV sigma, and an overvoltage trip point of 1.22 V with 12 mV sigma, demonstrated on Intel 4 silicon prototype. The design operates without any filter cap, allowing a fast, power-on ramp of <inline-formula> <tex-math>$2~\\\\mu $ </tex-math></inline-formula>s, and brown-out detection of <200 ns. A voltage band detection of 0.48–1.22 V is enabled through a finite-state machine (FSM) to modify CP and LDO gain depending on input voltage.\",\"PeriodicalId\":13032,\"journal\":{\"name\":\"IEEE Solid-State Circuits Letters\",\"volume\":\"8 \",\"pages\":\"157-160\"},\"PeriodicalIF\":2.0000,\"publicationDate\":\"2025-03-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Solid-State Circuits Letters\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/11008796/\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Solid-State Circuits Letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/11008796/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
A Bandgap Diode-Based Voltage Band Detection Circuit With Fast Response Time and Low Vmin on Intel 4 Logic Technology
A fast, accurate, single-rail voltage detection circuit (VDC) is presented. Low voltage operation is achieved by a variable gain Charge Pump (CP) followed by a Low-Dropout regulator (LDO). An Open-loop band gap reference (BGREF), passed to a dynamic comparator, achieves an undervoltage trip point of 0.62 V with 8.7 mV sigma, and an overvoltage trip point of 1.22 V with 12 mV sigma, demonstrated on Intel 4 silicon prototype. The design operates without any filter cap, allowing a fast, power-on ramp of $2~\mu $ s, and brown-out detection of <200 ns. A voltage band detection of 0.48–1.22 V is enabled through a finite-state machine (FSM) to modify CP and LDO gain depending on input voltage.