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IEEE Solid-State Circuits Letters最新文献

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A 1.2-V, 8.5-ns Settling, Bi-Slewing CMOS Driver for Heavy Loads in Discrete-Time Analog Computing Applications 一个1.2 v， 8.5 ns沉降，双回转CMOS驱动器在离散时间模拟计算应用的重负载
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-07-28 DOI: 10.1109/LSSC.2026.3717852
Maysara Hamada;Mostafa Toubar;Zixu Wang;Nishant Bakshi;Hsiang-Chun Cheng;Mayank Palaria;Joshua Yang;Mike Shuo-Wei Chen
{"title":"A 1.2-V, 8.5-ns Settling, Bi-Slewing CMOS Driver for Heavy Loads in Discrete-Time Analog Computing Applications","authors":"Maysara Hamada;Mostafa Toubar;Zixu Wang;Nishant Bakshi;Hsiang-Chun Cheng;Mayank Palaria;Joshua Yang;Mike Shuo-Wei Chen","doi":"10.1109/LSSC.2026.3717852","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3717852","url":null,"abstract":"As crossbar-based analog computing grows in popularity for high-speed, energy-efficient processing, the need to drive discrete-time signals to heavy loads arises. This letter presents a novel bi-slewing CMOS driver utilizing high slew-rate error amplifiers and a push–pull stage. The proposed driver achieves a measured settling time of 8.5 ns and a total harmonic distortion (THD) of −50 dBc while driving a 15-<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula> load and consuming 7 mA from a 1.2-V supply, enabling monolithic or heterogeneous integration with commercial crossbars.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"218-221"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148747390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 27.5–28.5 mJ/Frame 3-D Gaussian Rendering Processor With Spherical Beta Illumination and Mixed-Precision Computation Path 一种27.5-28.5 mJ/帧球面Beta照明和混合精度计算路径的三维高斯渲染处理器
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-03-23 DOI: 10.1109/LSSC.2026.3676726
Cheng Nian;Xiaorui Mo;Jiaqi Zhang;Fasih Ud Din Farrukh;Jiaying Peng;Fei Chen;Chun Zhang
{"title":"A 27.5–28.5 mJ/Frame 3-D Gaussian Rendering Processor With Spherical Beta Illumination and Mixed-Precision Computation Path","authors":"Cheng Nian;Xiaorui Mo;Jiaqi Zhang;Fasih Ud Din Farrukh;Jiaying Peng;Fei Chen;Chun Zhang","doi":"10.1109/LSSC.2026.3676726","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3676726","url":null,"abstract":"This letter presents a 3-D Gaussian rendering processor that integrates a spherical beta (SB) illumination module with a mixed-precision rendering engine to enable energy-efficient novel-view synthesis on edge devices. SB replaces spherical harmonics (SH) with a hardware-efficient kernel implemented using a pipelined fixed-point piecewise linear (PWL) power unit. The pipeline uses FP16 for preprocessing and fixed-point arithmetic for rasterization and blending with a lightweight exponential LUT. Implemented with light configuration on Xilinx ZCU104 at 200–250 MHz, the design achieves 34.12 dB PSNR and 116–138 FPS at <inline-formula> <tex-math>$800times 800$ </tex-math></inline-formula> resolution with 3.21–3.85 W power (27.7–27.9 mJ/frame). It delivers higher image quality and up to <inline-formula> <tex-math>$2times $ </tex-math></inline-formula> better energy efficiency than prior FPGA accelerators, while maintaining competitive resource usage.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"113-116"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147606206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An IEEE802.15.4a/z/ab Compatible IR-UWB 2TRX With Full-Duplex Radar Sensing and Aliasing Suppressing Semisynchronous TX 兼容ieee802.15.a /z/ab的全双工雷达传感和抑制混叠的IR-UWB 2TRX半同步传输
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-03-27 DOI: 10.1109/LSSC.2026.3697493
Anoop Narayan Bhat;Erwin Allebes;Elbert Bechthum;Zule Xu;Stan van der Ven;Mohieddine El Soussi;Johan van Den Heuvel;Paul van Zeijl;Paul Mateman;Murat Eskiyerli;Stefano Traferro;Amirashkan Farsaei;Evgenii Tiurin;Sahan Gamage;Pepijn Boer;Igor Petrov;Jochem Govers;Huib Visser;Martijn Hijdra;Sharada Prasad Shantharam;Ivo Marques;Gururaja Kasanadi Ramachandra;Kaijie Ding;Ran Li;Aasish Boora;Peter Vis;Mario Konijnenburg;Arjan Breeschoten;Peng Zhang;Yao-Hong Liu;Christian Bachmann
{"title":"An IEEE802.15.4a/z/ab Compatible IR-UWB 2TRX With Full-Duplex Radar Sensing and Aliasing Suppressing Semisynchronous TX","authors":"Anoop Narayan Bhat;Erwin Allebes;Elbert Bechthum;Zule Xu;Stan van der Ven;Mohieddine El Soussi;Johan van Den Heuvel;Paul van Zeijl;Paul Mateman;Murat Eskiyerli;Stefano Traferro;Amirashkan Farsaei;Evgenii Tiurin;Sahan Gamage;Pepijn Boer;Igor Petrov;Jochem Govers;Huib Visser;Martijn Hijdra;Sharada Prasad Shantharam;Ivo Marques;Gururaja Kasanadi Ramachandra;Kaijie Ding;Ran Li;Aasish Boora;Peter Vis;Mario Konijnenburg;Arjan Breeschoten;Peng Zhang;Yao-Hong Liu;Christian Bachmann","doi":"10.1109/LSSC.2026.3697493","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3697493","url":null,"abstract":"This letter presents an 802.15.4ab/a/z compatible IR-UWB 2TRX highlighting a full-duplex-based radar, a semisynchronous TX and TRX’s digital baseband. A capacitive tuning technique proposed in the electrical balance duplexer (EBD)-based duplex RF front-end (RF-FE) improves TX-antenna insertion loss by 1.4 dB and the sensitivity of TX–RX isolation by 3.4 dB. The TRX achieves > 30-dB isolation while transmitting 500-MHz pulses centered at 8 GHz over 2VSWR antenna variation. The proposed asynchronous first-order-hold (FoH) switched-capacitor power amplifier (SCPA) with a delay-locked-loop (DLL)-based calibration in TX achieves <inline-formula> <tex-math>$lt -50$ </tex-math></inline-formula> dBr alias sidelobes, 5 dB lower compared to the state-of-the-art (SoTA). The digital baseband supports next generation 802.15.4ab’s sensing packets (SENS) and high-data-rate (HDR) mode. The 2TRX is implemented on a 22-nm CMOS process.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"190-193"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148442261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 58.9–73.7-GHz Quadrature Dual-Core Class-F₃,₅ Oscillator With Tail-Assisted Implicit Quintupling 58.9 - 73.7 ghz正交双核f类₃，₅振荡器，带有尾辅助隐式五倍器
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-06-03 DOI: 10.1109/LSSC.2026.3699799
Yevhenii Mormul;Patchara Sawakewang;Sayan Kumar;Chawin Khongprasongsiri;Teerachot Siriburanon;Robert Bogdan Staszewski
{"title":"A 58.9–73.7-GHz Quadrature Dual-Core Class-F₃,₅ Oscillator With Tail-Assisted Implicit Quintupling","authors":"Yevhenii Mormul;Patchara Sawakewang;Sayan Kumar;Chawin Khongprasongsiri;Teerachot Siriburanon;Robert Bogdan Staszewski","doi":"10.1109/LSSC.2026.3699799","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3699799","url":null,"abstract":"We introduce a new class-F3,5 oscillator topology that enables quadrature operation by duplicating a conventional class-F3 oscillator core and electromagnetically coupling the two cores through a pair of additional coils feeding source terminals of the <inline-formula> <tex-math>$g_{m}$ </tex-math></inline-formula> transistors. The coupling network enhances the fifth-harmonic component, enabling efficient extraction and quadrature operation across the 58.9–73.7-GHz mm-wave frequency range (22.6%). Fabricated in 22 nm FD-SOI, the class-F3,5 oscillator achieves an average phase noise of –124.4 dBc/Hz at a 10 MHz offset, resulting in 188/195 dB FoM/FoMT.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"198-201"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11550156","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148489107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Sampling PLL With Boosted Phase Detection Gain Achieving 52 fs RMS Jitter and 110.4 MHz Lock-In Range 一种相位检测增益增强的采样锁相环，实现52 fs RMS抖动和110.4 MHz锁定范围
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-07-07 DOI: 10.1109/LSSC.2026.3710778
Hyogyoung An;Changmin An;Sungjin Kim;Heein Yoon
{"title":"A Sampling PLL With Boosted Phase Detection Gain Achieving 52 fs RMS Jitter and 110.4 MHz Lock-In Range","authors":"Hyogyoung An;Changmin An;Sungjin Kim;Heein Yoon","doi":"10.1109/LSSC.2026.3710778","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3710778","url":null,"abstract":"This work presents a sampling phase-locked loop (SPLL) that simultaneously achieves sub-sampling SPLL (SSPLL)-level jitter and wide lock-in range (<inline-formula> <tex-math>$f_{mathbf {lock}}$ </tex-math></inline-formula>) inherent to SPLL architecture. By employing a high phase detection gain, the proposed SPLL ensures low in-band phase noise (PN) dominated by reference, while maintaining robust re-locking without an auxiliary frequency-locked loop (FLL). Fabricated in a 65-nm CMOS process, the proposed SPLL achieves an RMS jitter of 52 fs, and <inline-formula> <tex-math>$f_{mathbf {lock}}$ </tex-math></inline-formula> of 110.4 MHz, occupying only 0.12 mm2 and consuming 10.2 mW. As a result, it offers a low-noise and robust frequency synthesis solution.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"202-205"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148625947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A High-Efficiency Magnetoelectric Power Link With a Load-Adaptive CMOS Rectifier for Miniaturized Implants 基于负载自适应CMOS整流器的小型植入物高效磁电电源链
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-03-31 DOI: 10.1109/LSSC.2026.3679620
Yasemin Engür;Mingxiang Gao;Niels Kuster;Mahsa Shoaran
{"title":"A High-Efficiency Magnetoelectric Power Link With a Load-Adaptive CMOS Rectifier for Miniaturized Implants","authors":"Yasemin Engür;Mingxiang Gao;Niels Kuster;Mahsa Shoaran","doi":"10.1109/LSSC.2026.3679620","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3679620","url":null,"abstract":"Miniaturized biomedical implants are currently constrained by limited wireless power transfer (WPT) efficiency under load variation and spatial misalignment. This work presents a custom magnetoelectric (ME) power link incorporating a load-adaptive CMOS rectifier to address these challenges. By employing a current sensing control loop for dynamic switch sizing and delay compensation, the proposed architecture achieves a peak power conversion efficiency (PCE) of 97.25% and sustains >93.4% efficiency over a wide output power range from <inline-formula> <tex-math>$150~mu $ </tex-math></inline-formula>W to 8 mW. Fabricated in 65-nm CMOS, the <inline-formula> <tex-math>$0.25~text {mm}^{2}$ </tex-math></inline-formula> chip interfaces with a custom 362-kHz ME transducer (<inline-formula> <tex-math>$5times ~2times ~2~text {mm}^{3}$ </tex-math></inline-formula>), providing a 1.2-V output with only 20-mV ripple across a 1-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>F load capacitor. System-level validation through in vitro tissue measurements and numerical simulations confirms robust operation and compliance with ICNIRP electromagnetic exposure limits. The proposed system achieves a state-of-the-art normalized output power of <inline-formula> <tex-math>$216~mu $ </tex-math></inline-formula>W per unit magnetic field (1 Oe), demonstrating a high-efficiency power delivery solution for miniaturized implantable devices.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"125-128"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147665217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Logic-Compatible 2-Transistor Embedded Bipolar RRAM MACRO: A 28-nm Multiple-Time Programmable (MTP) Memory Without Extra Masks 一个逻辑兼容的2晶体管嵌入式双极RRAM宏：一个28纳米多时间可编程（MTP）存储器没有额外的掩模
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-03-18 DOI: 10.1109/LSSC.2026.3675063
Yi Xiang Huang;Y. S. Lin;P. S. Huang;E. Ray Hsieh
{"title":"A Logic-Compatible 2-Transistor Embedded Bipolar RRAM MACRO: A 28-nm Multiple-Time Programmable (MTP) Memory Without Extra Masks","authors":"Yi Xiang Huang;Y. S. Lin;P. S. Huang;E. Ray Hsieh","doi":"10.1109/LSSC.2026.3675063","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3675063","url":null,"abstract":"This letter presents a 2-transistor (2T) bipolar embedded resistive RAM (eRRAM) MACRO fabricated in a 28-nm high-k metal gate (HKMG) process for multitime programmable (MTP) applications. To overcome the scaling bottlenecks of traditional embedded Flash, this work utilizes an extra-mask-free, pure front-end-of-line (FEOL) integration, offering a robust solution for automotive and industrial SoCs at and beyond the 28-nm node. The unit cell architecture, read/write operations, and a low-power sense amplifier design are characterized. Experimental results for a 2-kb MACRO demonstrate 1000-cycle endurance with a sensing window over three-folds and data retention surpassing 1000 h at <inline-formula> <tex-math>$150~^{circ }$ </tex-math></inline-formula>C.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"117-120"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147665299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.68 nJ/solution Inverse-Matrix-Vector Multiplication Solver With Decoupled Input Injection Scheme in 65-nm CMOS 基于解耦输入注入的65纳米CMOS反矩阵-矢量乘法求解器
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-07-28 DOI: 10.1109/LSSC.2026.3717659
Hsiang-Chun Cheng;Mayank Palaria;Qiaochu Zhang;Shiyu Su;Mike Shuo-Wei Chen
{"title":"A 0.68 nJ/solution Inverse-Matrix-Vector Multiplication Solver With Decoupled Input Injection Scheme in 65-nm CMOS","authors":"Hsiang-Chun Cheng;Mayank Palaria;Qiaochu Zhang;Shiyu Su;Mike Shuo-Wei Chen","doi":"10.1109/LSSC.2026.3717659","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3717659","url":null,"abstract":"This letter presents an analog inverse-matrix-vector multiplication (IMVM) solver that addresses the input loading limitation of prior crossbar-based implementations. The proposed decoupled input injection scheme isolates the input circuit from the crossbar array, enabling the use of smaller crossbar conductance for lower power consumption and relaxing the required op amp gain by up to <inline-formula> <tex-math>$16times $ </tex-math></inline-formula> across different impedance coupling factors (ICFs). A programmable crossbar feedback network further supports both square and nonsquare matrix equation solving. A 65-nm prototype achieves an average energy of 0.68 nJ/solution under a 1-V core supply for <inline-formula> <tex-math>$8times 8$ </tex-math></inline-formula> IMVM problems. It demonstrates <inline-formula> <tex-math>$20times $ </tex-math></inline-formula> lower energy compared to the state-of-the-art analog solver, evaluated at equivalent problem size and 6.5-bit accuracy constraint with well-conditioned matrix problems.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"222-225"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148747113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An 800-MS/s 13-b 2× TI Pipelined-SAR ADC With Rapid Digital Amplification 具有快速数字放大的800-MS/s 13-b 2× TI管道sar ADC
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-04-16 DOI: 10.1109/LSSC.2026.3684735
Peizhe Li;Danfeng Zhai;Qi Liu;Chixiao Chen
{"title":"An 800-MS/s 13-b 2× TI Pipelined-SAR ADC With Rapid Digital Amplification","authors":"Peizhe Li;Danfeng Zhai;Qi Liu;Chixiao Chen","doi":"10.1109/LSSC.2026.3684735","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3684735","url":null,"abstract":"This work proposes a rapid digital amplification (RDA) with residue-aware reference, offering an equivalent open-loop (OL) gain enhancement of 25 dB and reducing the interstage gain error (ISGE)-induced SNR degradation by 20 dB, with an extra amplification latency of only 200 ps. It is implemented in an 800-MS/s 13-b two-way time-interleaved (TI) pipelined-successive-approximation-register (pipelined-SAR) analog-to-digital converter (ADC). The ADC exhibits only 2.6-dB signal-to-noise and distortion ratio (SNDR) variation across different temperatures and supply voltages without requiring additional ISGE calibration. The prototype ADC is implemented in a 28-nm CMOS process and consumes 11.44 mW under 800 MS/s. The measured SNDR and spurious free dynamic range (SFDR) with 345-MHz input are 64.69 and 76.78 dB, respectively, leading to a Schreier figure-of-merit (FoM) of 170.13 dB.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"137-140"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147796102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Corrections to “Opal: A 16-nm Coarse-Grained Reconfigurable Array SoC for Full Sparse Machine Learning Applications” 更正“Opal：用于全稀疏机器学习应用的16纳米粗粒度可重构阵列SoC”
IF 2
IEEE Solid-State Circuits Letters Pub Date : 2026-01-01 Epub Date: 2026-04-28 DOI: 10.1109/LSSC.2026.3683139
Po-Han Chen;Bo Wun Cheng;Michael Oduoza;Zhouhua Xie;Rupert Lu;Sai Gautham Ravipati;Kalhan Koul;Alex Carsello;Yuchen Mei;Mark Horowitz;Priyanka Raina
{"title":"Corrections to “Opal: A 16-nm Coarse-Grained Reconfigurable Array SoC for Full Sparse Machine Learning Applications”","authors":"Po-Han Chen;Bo Wun Cheng;Michael Oduoza;Zhouhua Xie;Rupert Lu;Sai Gautham Ravipati;Kalhan Koul;Alex Carsello;Yuchen Mei;Mark Horowitz;Priyanka Raina","doi":"10.1109/LSSC.2026.3683139","DOIUrl":"https://doi.org/10.1109/LSSC.2026.3683139","url":null,"abstract":"Presents corrections to the paper, (Opal: A 16-nm Coarse-Grained Reconfigurable Array SoC for Full Sparse Machine Learning Applications).","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"141-141"},"PeriodicalIF":2.0,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11498552","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147796146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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