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IEEE Solid-State Circuits Letters最新文献

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A 33.06-Gb/s Reconfigurable Galois Field oFEC Decoder for Optical Intersatellite Communication 用于卫星间光学通信的 33.06 Gb/s 可重构伽罗瓦场 oFEC 解码器
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-10-24 DOI: 10.1109/LSSC.2024.3486234
Xiangdong Wei;Yufan Yue;Seungkyu Choi;Tutu Ajayi;Ronald Dreslinski;David Blaauw;Hun-Seok Kim
{"title":"A 33.06-Gb/s Reconfigurable Galois Field oFEC Decoder for Optical Intersatellite Communication","authors":"Xiangdong Wei;Yufan Yue;Seungkyu Choi;Tutu Ajayi;Ronald Dreslinski;David Blaauw;Hun-Seok Kim","doi":"10.1109/LSSC.2024.3486234","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3486234","url":null,"abstract":"We introduce a high-throughput reconfigurable forward error correction (FEC) decoder capable of decoding BCH, RS, and open FEC (oFEC) codes. With a reconfigurable BCH inner code, the proposed decoder in the oFEC mode provides a wide range of coding gain and throughput to enable efficient and reliable intersatellite optical communication. It features unprecedented reconfigurability for BCH/RS codes in terms of Galois field (GF) size, code length, code rate, and parallel factor, providing tradeoffs between error correction performance, energy, and throughput. Fabricated in 12-nm CMOS technology, the decoder achieves a throughput of 33.06 Gb/s, energy efficiency of 40.35 pJ/b, and a net coding gain of 7.27 dB at \u0000<inline-formula> <tex-math>$10^{text {-6}}$ </tex-math></inline-formula>\u0000 BER with an oFEC code using inner BCH(256, 223).","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"331-334"},"PeriodicalIF":2.2,"publicationDate":"2024-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142595128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Time-Modulated-LO-Path Vector Modulators for Beamforming Receivers 用于波束成形接收器的时间调制-LO-路径矢量调制器
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-10-11 DOI: 10.1109/LSSC.2024.3478837
Petar Barac;Matthew Bajor;Peter R. Kinget
{"title":"Time-Modulated-LO-Path Vector Modulators for Beamforming Receivers","authors":"Petar Barac;Matthew Bajor;Peter R. Kinget","doi":"10.1109/LSSC.2024.3478837","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3478837","url":null,"abstract":"A time-modulated LO (TM-LO) vector modulator (VM) architecture using a time domain approach for amplitude scaling and phase shifting received signals is presented. The TM-LO uses rail-to-rail LO waveforms generated from digitally synthesized blocks and pass-gate switches to perform the amplitude/phase control. A single element receiver achieves 0.2 dB RMS gain error and 1.4° RMS phase error with 5 bits of amplitude/phase resolution across a 360° range is implemented in a 65 nm CMOS process. Without time-modulation, the hardware is capable of 3-bits of resolution. The inherent digital nature of TM-LO architecture provides opportunity very compact front-ends suitable for large arrays and lower voltage technologies. Four TM-LO chips were used to create a beamforming receiver","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"323-326"},"PeriodicalIF":2.2,"publicationDate":"2024-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142517990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 1–3 GHz Fast-Locking Frequency Synthesizer Based on a Combination of PLL and MDLL With Auto-Zero Phase-Error Compensation 基于 PLL 和 MDLL 组合的 1-3 GHz 快速锁定频率合成器，具有自动零相位误差补偿功能
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-10-11 DOI: 10.1109/LSSC.2024.3478799
Ching-Yuan Yang;Hao-Cheng Hsu;Ping-Heng Wu;Samuel Palermo
{"title":"A 1–3 GHz Fast-Locking Frequency Synthesizer Based on a Combination of PLL and MDLL With Auto-Zero Phase-Error Compensation","authors":"Ching-Yuan Yang;Hao-Cheng Hsu;Ping-Heng Wu;Samuel Palermo","doi":"10.1109/LSSC.2024.3478799","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3478799","url":null,"abstract":"A fast-locking low-jitter hybrid frequency synthesizer using a charge-pump phase-locked loop (CP-PLL) and a multiplying delay-locked loop (MDLL) is presented. The CP-PLL uses a discriminator-aided detector (DAD) to alleviate the cycle-slipping issue and an auto-zero phase error compensator (AZ-PEC) to compensate the accumulated phase error during frequency acquisition to enhance the settling time. Then, the MDLL overcomes the jitter accumulation of CP-PLL. The synthesizer was fabricated in a 90-nm CMOS process. The output frequency ranges from 1 to 3 GHz. When switching from 1 to 2.5 GHz, the measured settling time using DAD and AZ-PEC is 520 ns, which is approximately 26 reference clock cycles. The power consumption is 12 mW at 2.5 GHz for a supply of 1.2 V. The integral root-mean-square jitter over 1 kHz–100 MHz is 1.62 ps.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"315-318"},"PeriodicalIF":2.2,"publicationDate":"2024-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142517989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Digital SRAM-Based Computing-in-Memory Macro Supporting Parallel Maintaining for Network Management 基于数字 SRAM 的计算内存宏，支持并行维护网络管理
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-10-10 DOI: 10.1109/LSSC.2024.3477619
Geng Li;Hanqing Zheng;Jiacong Sun;Hailong Jiao
{"title":"A Digital SRAM-Based Computing-in-Memory Macro Supporting Parallel Maintaining for Network Management","authors":"Geng Li;Hanqing Zheng;Jiacong Sun;Hailong Jiao","doi":"10.1109/LSSC.2024.3477619","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3477619","url":null,"abstract":"A digital SRAM-based computing-in-memory (CIM) macro is proposed to enable parallel maintaining for statistics counters in network management. A new 18-transistor bit-cell is designed to support in-situ counter maintaining. A joint coding scheme and a daisy-chain circuit are leveraged to enhance the throughput as well as reduce the computing energy consumption and area. The proposed CIM macro saves \u0000<inline-formula> <tex-math>$6.9times $ </tex-math></inline-formula>\u0000 in energy at 1.2 V and \u0000<inline-formula> <tex-math>$2.33times $ </tex-math></inline-formula>\u0000 in area compared with the conventional statistics counters in a 55-nm CMOS technology.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"327-330"},"PeriodicalIF":2.2,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142587641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An 8-nm 20-Gb/s/pin Single-Ended PAM-4 Transceiver With Pre/Post-Channel Switching Jitter Compensation and DQS-Driven Biasing 具有前/后通道切换抖动补偿和 DQS 驱动偏置功能的 8 纳米 20-Gb/s/pin 单端 PAM-4 收发器
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-10-10 DOI: 10.1109/LSSC.2024.3477736
Kyunghwan Min;Jahoon Jin;Soo-Min Lee;Sodam Ju;Jisu Yook;Jihoon Lee;Yunji Hong;Sung-Sik Park;Sang-Ho Kim;Jongwoo Lee;Hyungjong Ko
{"title":"An 8-nm 20-Gb/s/pin Single-Ended PAM-4 Transceiver With Pre/Post-Channel Switching Jitter Compensation and DQS-Driven Biasing","authors":"Kyunghwan Min;Jahoon Jin;Soo-Min Lee;Sodam Ju;Jisu Yook;Jihoon Lee;Yunji Hong;Sung-Sik Park;Sang-Ho Kim;Jongwoo Lee;Hyungjong Ko","doi":"10.1109/LSSC.2024.3477736","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3477736","url":null,"abstract":"This letter presents a 20-Gb/s/pin single-ended pulse amplitude modulation (PAM)-4 transceiver implemented in an 8-nm CMOS process, featuring an advanced switching jitter compensation (SWJC) technique and a DQS-driven amplifier bias generation method for a source-synchronous clocking system, aimed for next-generation low-power memory interfaces utilizing multilevel signaling. The proposed prechannel SWJC (pre-SWJC) in the transmitter adjusts the input edge timing of the thermometer PAM-4 driver to control the transitions of the PAM-4 signal. This transition control advances the outermost transitions, thereby not only minimizing the switching jitter (SWJ) of the middle eye but also enhancing the effectiveness of the post-channel SWJC (post-SWJC) performed at the receiver. Ultimately, the comprehensive solution combining the proposed pre/post-SWJC improved the timing margin from 0.26 UI to 0.39 UI at a BER of 1e-12, with only a 4.5% increase in power consumption and a 0.59% area overhead. Additionally, the proposed DQS-driven biasing technique in the receiver supplies biases for the amplifiers in the data lanes by utilizing the common-mode feedback of the replica amplifier in the differential clock lane. This approach reduces variation sources compared to the self-biasing structure that uses common-mode feedback in the data lanes, thereby improving the standard deviation of the amplifier’s bias voltage and gain variation by 58.3%.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"319-322"},"PeriodicalIF":2.2,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142517783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
0.6-V, μW-Power Four-Stage OTA With Minimal Components, and 100× Load Range 0.6 V、μW 功率四级 OTA，元件最少，负载范围达 100 倍
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-10-08 DOI: 10.1109/LSSC.2024.3476194
Marco Privitera;Alfio Dario Grasso;Andrea Ballo;Massimo Alioto
{"title":"0.6-V, μW-Power Four-Stage OTA With Minimal Components, and 100× Load Range","authors":"Marco Privitera;Alfio Dario Grasso;Andrea Ballo;Massimo Alioto","doi":"10.1109/LSSC.2024.3476194","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3476194","url":null,"abstract":"A four-stage operational transconductance amplifier (OTA) for ultralow-power applications is introduced in this letter. The proposed circuit inclusive of frequency compensation requires minimal transistor count and passives, overcoming the traditionally difficult compensation of four-stage OTAs and bringing it back to the simplicity of three-stage OTAs. At the same time, the proposed circuit achieves high power efficiency, as evidenced by the >\u0000<inline-formula> <tex-math>$3.7times $ </tex-math></inline-formula>\u0000 (>\u0000<inline-formula> <tex-math>$11.3times $ </tex-math></inline-formula>\u0000) improvement in the large-signal (small-signal) power efficiency figure of merit \u0000<inline-formula> <tex-math>${mathrm { FOM}}_{L}~({mathrm { FOM}}_{S})$ </tex-math></inline-formula>\u0000, compared to prior four-stage OTAs (sub-1 V multistage OTAs). Thanks to the lower sensitivity of the phase margin to the load capacitance, the proposed OTA remains stable under a wide range of loads (double-sided as in any three- and four-stage OTA), achieving a max/min ratio of the load capacitance of >\u0000<inline-formula> <tex-math>$100times $ </tex-math></inline-formula>\u0000.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"311-314"},"PeriodicalIF":2.2,"publicationDate":"2024-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142452674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Broadband GaN MMIC Doherty Power Amplifier Using Compact Short-Circuited Coupler 使用紧凑型短路耦合器的宽带 GaN MMIC Doherty 功率放大器
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-10-01 DOI: 10.1109/LSSC.2024.3471855
Shun Wan;Wenhua Chen;Guansheng Lv;Yuhang Zhang;Xu Shi;Zhenghe Feng
{"title":"Broadband GaN MMIC Doherty Power Amplifier Using Compact Short-Circuited Coupler","authors":"Shun Wan;Wenhua Chen;Guansheng Lv;Yuhang Zhang;Xu Shi;Zhenghe Feng","doi":"10.1109/LSSC.2024.3471855","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3471855","url":null,"abstract":"In this letter, a broadband gallium nitride (GaN) monolithic microwave integrated circuit Doherty power amplifier (DPA) using a compact short-circuited coupler (CSC) is presented. To enhance the bandwidth and reduce the size of integrated DPA, the conventional \u0000<inline-formula> <tex-math>$lambda $ </tex-math></inline-formula>\u0000/2 transmission line in the peaking output matching network is replaced by the CSC structure. Detailed theoretical analysis and design procedures are provided. Based on the proposed solution, a 5.1–7.2-GHz DPA is designed using a 0.12-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m GaN HEMT process. The fractional bandwidth (FBW) is 34.1%. The measurement results show a saturated output power of 37.2–39 dBm and a 6-dB back-off drain efficiency of 38.4%–50.5% across the design bands with a chip size of \u0000<inline-formula> <tex-math>$2.6times 2$ </tex-math></inline-formula>\u0000.6 mm. The adjacent channel power ratio (ACPR) under 100-MHz single-carrier 64 QAM modulation signal with a 6-dB peak-to-average power ratio (PAPR) excitation is better than −45 dBc with digital predistortion (DPD).","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"307-310"},"PeriodicalIF":2.2,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142452698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 12 V Compliant Multichannel Dual Mode Neural Stimulator With 0.004% Charge Mismatch and a 4×VDD Tolerant On-Chip Discharge Switch in Low-Voltage CMOS 符合 12 V 标准的多通道双模式神经刺激器，电荷失配率为 0.004%，采用低压 CMOS，具有 4×VDD 容限的片上放电开关
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-09-25 DOI: 10.1109/LSSC.2024.3467341
Thanh Dat Nguyen;Alessandro Maggi;Gianluca Lazzi;Constantine Sideris
{"title":"A 12 V Compliant Multichannel Dual Mode Neural Stimulator With 0.004% Charge Mismatch and a 4×VDD Tolerant On-Chip Discharge Switch in Low-Voltage CMOS","authors":"Thanh Dat Nguyen;Alessandro Maggi;Gianluca Lazzi;Constantine Sideris","doi":"10.1109/LSSC.2024.3467341","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3467341","url":null,"abstract":"This letter presents a 12 V-compliant 4-channel neural stimulator fabricated in a low-voltage bulk CMOS process. Arrays of current memory cells are used to implement anodic and cathodic current sources to generate anodic and cathodic current ratios that are robust to process-voltage-temperature variations. A novel, fully integrated discharge switch is presented that tolerates an output voltage up to \u0000<inline-formula> <tex-math>$4times V_{DD}$ </tex-math></inline-formula>\u0000, which is the highest reported for low-voltage bulk CMOS monopolar stimulators. The proposed neural stimulator can operate in both constant current mode (CCM) with a \u0000<inline-formula> <tex-math>$1~mu $ </tex-math></inline-formula>\u0000-1.2 mA output current range and constant voltage mode (CVM) with a 1–11 V output voltage range. The output waveform is fully programmable, including cathodic and anodic amplitudes and ratios designed to have excellent charge balancing with only 0.004% charge mismatch.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"283-286"},"PeriodicalIF":2.2,"publicationDate":"2024-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142438490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 14 nm MRAM-Based Multi-bit Analog In-Memory Computing With Process-Variation Calibration for 72 Macros-Based Accelerator 基于 14 纳米 MRAM 的多比特模拟内存计算，可对 72 个基于宏的加速器进行过程变化校准
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-09-23 DOI: 10.1109/LSSC.2024.3465595
Sungmeen Myung;Seok-Ju Yun;Minje Kim;Wooseok Yi;Jaehyuk Lee;Jangho An;Kyoung-Rog Lee;Chang-Woo Shin;Seungchul Jung;Soonwan Kwon
{"title":"A 14 nm MRAM-Based Multi-bit Analog In-Memory Computing With Process-Variation Calibration for 72 Macros-Based Accelerator","authors":"Sungmeen Myung;Seok-Ju Yun;Minje Kim;Wooseok Yi;Jaehyuk Lee;Jangho An;Kyoung-Rog Lee;Chang-Woo Shin;Seungchul Jung;Soonwan Kwon","doi":"10.1109/LSSC.2024.3465595","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3465595","url":null,"abstract":"This letter presents an analog in-memory computing (IMC) macro utilizing 14 nm MRAM technology. To facilitate energy-efficient high-throughput multiply accumulate (MAC) operations, a multi-bit weight is introduced using stacked magnetic tunnel junction architecture and an analog bit-parallel MAC (ABP-MAC) scheme is proposed. This approach delivers 3.3 times better TOPS/mm2 than the state-of-the-art MRAM-based IMC macro. Additionally, a comprehensive calibration technique significantly improves computational accuracy across 72 IMC macros. The proposed IMC macro achieves 18.29 TOPS/mm2 and 340.8 TOPS/W with 1-bit normalization and classification accuracy of 90.2% with the Google speech commands dataset.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"295-298"},"PeriodicalIF":2.2,"publicationDate":"2024-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142430726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
S2D-CIM: SRAM-Based Systolic Digital Compute-in-Memory Framework With Domino Data Path Supporting Flexible Vector Operation and 2-D Weight Update S2D-CIM：基于 SRAM 的收缩式内存数字计算框架，采用多米诺数据路径，支持灵活的矢量操作和二维权重更新
IF 2.2
IEEE Solid-State Circuits Letters Pub Date : 2024-09-19 DOI: 10.1109/LSSC.2024.3463697
Meng Wu;Wenjie Ren;Peiyu Chen;Wentao Zhao;Tianyu Jia;Le Ye
{"title":"S2D-CIM: SRAM-Based Systolic Digital Compute-in-Memory Framework With Domino Data Path Supporting Flexible Vector Operation and 2-D Weight Update","authors":"Meng Wu;Wenjie Ren;Peiyu Chen;Wentao Zhao;Tianyu Jia;Le Ye","doi":"10.1109/LSSC.2024.3463697","DOIUrl":"https://doi.org/10.1109/LSSC.2024.3463697","url":null,"abstract":"In this letter, we propose an SRAM-based systolic digital compute-in-memory (S2D-CIM) framework which enables flexible input dataflow and mapping strategy to enhance the effective energy efficiency (EE), area efficiency, and writing bandwidth for practical CIM with innovations: 1) multistage domino data path (DDP); 2) a configurable asynchronous timing scheme; and 3) a 2-D burst writing scheme. The proposed S2D-CIM is fabricated using TSMC 22-nm technology and achieves 9.19 and 24.4 TOPS/W peak EE in systolic mode and broadcast mode, respectively, at full precision of 8-bit input, 8-bit weight, and 21-bit output. Compared with state of the arts, it achieves \u0000<inline-formula> <tex-math>$1.67times $ </tex-math></inline-formula>\u0000 effective EE improvement. Thanks to reusing introduced DDP, fast 2-D weight update is realized and gains 1.187 Tb/s writing bandwidth, which is \u0000<inline-formula> <tex-math>$14.3times $ </tex-math></inline-formula>\u0000 better than that of normal SRAM macro with the same capacity.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"291-294"},"PeriodicalIF":2.2,"publicationDate":"2024-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142438512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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