A 0.41-ns CLK-OUT Delay, 0.22-μVrms Input-Referred Noise CMOS Integration Dynamic Comparator With Flipping Capacitor for Charge Reuse

Abstract

A high-speed and power-efficient CMOS integration dynamic comparator is presented. Low-input-referred noise is accomplished by CMOS integration. To achieve low-power consumption, a charge-reusing scheme by flipping the flying capacitors across the pMOS/nMOS integration nodes is introduced. The 22-nm prototype achieves a 0.22- $\mu $ Vrms input-referred noise with an energy consumption of 227-fJ per conversion, which is improved by $2\times $ compared with the StrongARM counterpart in the same process. Furthermore, with the latch stage embedded, the achieved 0.41-ns CLK-OUT delay shows an over $20\times $ improvement compared with the existing works with CMOS integration.