Enhancing AI Acceleration: A Calibration-Free, PVT-Robust Analog Compute-in-Memory Macro With Activation Functions

Abstract

Most analog compute-in-memory (ACiM) works only focus on the multiple–accumulate (MAC) operation while neglecting the activation function (AF) in the digital domain. The frequent data conversion greatly reduces the benefits obtained by analog computing. This letter proposes an efficient 8-bit in-memory MAC with hybrid capacitor ladders. Then, a sparsity-aware R-2R DAC and an embedded SAR-ADC that reuses the capacitor ladders in the MAC are introduced to reduce the conversion overhead. Two on-chip AF schemes are included to further improve efficiency. Finally, differential signal path offers first-order PVT cancellation that improves computing accuracy and reduces the need for calibration.