{"title":"An 828-μW 100.9-dB SNDR 20-kHz BW Zoom-Linear-Exponential Incremental ADC With Split Positive Feedback and Duty-Cycle Amplifier","authors":"Lairong Fang;Shuwen Zhang;Xiaoyang Zeng;Zhiliang Hong;Jiawei Xu","doi":"10.1109/LSSC.2024.3510423","DOIUrl":null,"url":null,"abstract":"This letter presents a hybrid, three-step zoom-linear-exponential incremental analog-to-digital converter (ZLE-IADC) for audio applications. The zoom-SAR in the first step provides coarse signal quantization and relaxes the accuracy requirements of subsequent conversions. The second step utilizes a single-loop, first-order delta–sigma modulator (\n<inline-formula> <tex-math>$\\Delta \\Sigma $ </tex-math></inline-formula>\nM). In the third step, the \n<inline-formula> <tex-math>$\\Delta \\Sigma $ </tex-math></inline-formula>\nM is reconfigured as an exponential counting loop with split positive feedback (SPF). The SPF isolates the loop integrator from the residue sampling network, thereby improving the settling time of the residue amplifier (RA) under the transient switching of linear-exponential loads. Besides, a duty-cycle RA further reduces its average power from 48.4% to 6.1% of the IADC. Last, the zoom-SAR in the first step is reconfigured as a gain-embedded quantizer (GEQ) in the third step, optimizing the hardware cost. Fabricated in a standard 180-nm CMOS technology, the proposed IADC achieves a dynamic range (DR) of 103.9 dB and a signal-to-noise-and-distortion ratio (SNDR) of 100.9 dB, which corresponds to a state-of-the-art Schreier \n<inline-formula> <tex-math>${\\mathrm { FoM}}_{\\mathrm { S,{\\mathrm {DR}}}}$ </tex-math></inline-formula>\n of 177.7 dB.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"1-4"},"PeriodicalIF":2.2000,"publicationDate":"2024-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Solid-State Circuits Letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10772595/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
This letter presents a hybrid, three-step zoom-linear-exponential incremental analog-to-digital converter (ZLE-IADC) for audio applications. The zoom-SAR in the first step provides coarse signal quantization and relaxes the accuracy requirements of subsequent conversions. The second step utilizes a single-loop, first-order delta–sigma modulator (
$\Delta \Sigma $
M). In the third step, the
$\Delta \Sigma $
M is reconfigured as an exponential counting loop with split positive feedback (SPF). The SPF isolates the loop integrator from the residue sampling network, thereby improving the settling time of the residue amplifier (RA) under the transient switching of linear-exponential loads. Besides, a duty-cycle RA further reduces its average power from 48.4% to 6.1% of the IADC. Last, the zoom-SAR in the first step is reconfigured as a gain-embedded quantizer (GEQ) in the third step, optimizing the hardware cost. Fabricated in a standard 180-nm CMOS technology, the proposed IADC achieves a dynamic range (DR) of 103.9 dB and a signal-to-noise-and-distortion ratio (SNDR) of 100.9 dB, which corresponds to a state-of-the-art Schreier
${\mathrm { FoM}}_{\mathrm { S,{\mathrm {DR}}}}$
of 177.7 dB.