A 302.5-GHz 30.9-dB-Gain THz Amplifier in 65-nm CMOS

Abstract

A 302.5-GHz high-gain CMOS THz amplifier is proposed in this work. An electromagnetic (EM) modeling approach, verified by transistor measurements, is employed to optimize transistor layout, effectively reducing gate resistance and drain-to-gate capacitance. This significantly enhances the transistor’s maximum oscillation frequency $f_{\mathrm {\max }}$ from 239.7 to 367.5 GHz. Furthermore, a $G_{\mathrm {\max }}$ -peak-offset-matching technique is proposed to simultaneously optimize active transistors and passive matching networks, significantly increasing the gain by 3.5 dB. Implemented in a 65-nm CMOS technology, the proposed THz amplifier achieves a measured gain of 30.9 dB at 302.5 GHz with an output saturation power of –5.3 dBm while only consuming 35.4 mW from a 1.1 V supply. To the best of the authors’ knowledge, this work exhibits the first experimental validation of the EM modeling approach and achieves the highest reported gain above 200 GHz in bulk CMOS technologies.