{"title":"采用柔性氧化物TFT技术的低功耗全动态锁存比较器","authors":"Vaishali Choudhary;Pydi Ganga Bahubalindruni","doi":"10.1109/LSSC.2025.3557862","DOIUrl":null,"url":null,"abstract":"This letter presents a novel low-power, fully dynamic, latched comparator using only n-type, single-gate amorphous-indium-gallium-zinc-oxide thin-film transistors (a-IGZO TFTs) on a <inline-formula> <tex-math>$27~\\mu $ </tex-math></inline-formula>m thick polyimide substrate. This circuit demonstrates a stable performance up to an input signal frequency of 15 kHz with 1-MHz clock. By employing a pseudo-CMOS bootstrapped load, it achieved an output voltage swing of around 90%, an input-referred offset and noise voltages of 28 mV and 14 mV, respectively from measurements. In addition, it can reliably detect a minimum differential input voltage of 50 mV at a <inline-formula> <tex-math>$V_{\\mathrm { DD}}$ </tex-math></inline-formula> of 4 V, while consuming only <inline-formula> <tex-math>$8~\\mu $ </tex-math></inline-formula>W power. Therefore, this design is well-suited in biomedical wearable devices which typically needs low-power.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"101-104"},"PeriodicalIF":2.2000,"publicationDate":"2025-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Low-Power Fully Dynamic Latched Comparator Using Flexible Oxide TFT Technology\",\"authors\":\"Vaishali Choudhary;Pydi Ganga Bahubalindruni\",\"doi\":\"10.1109/LSSC.2025.3557862\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This letter presents a novel low-power, fully dynamic, latched comparator using only n-type, single-gate amorphous-indium-gallium-zinc-oxide thin-film transistors (a-IGZO TFTs) on a <inline-formula> <tex-math>$27~\\\\mu $ </tex-math></inline-formula>m thick polyimide substrate. This circuit demonstrates a stable performance up to an input signal frequency of 15 kHz with 1-MHz clock. By employing a pseudo-CMOS bootstrapped load, it achieved an output voltage swing of around 90%, an input-referred offset and noise voltages of 28 mV and 14 mV, respectively from measurements. In addition, it can reliably detect a minimum differential input voltage of 50 mV at a <inline-formula> <tex-math>$V_{\\\\mathrm { DD}}$ </tex-math></inline-formula> of 4 V, while consuming only <inline-formula> <tex-math>$8~\\\\mu $ </tex-math></inline-formula>W power. Therefore, this design is well-suited in biomedical wearable devices which typically needs low-power.\",\"PeriodicalId\":13032,\"journal\":{\"name\":\"IEEE Solid-State Circuits Letters\",\"volume\":\"8 \",\"pages\":\"101-104\"},\"PeriodicalIF\":2.2000,\"publicationDate\":\"2025-04-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Solid-State Circuits Letters\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10949609/\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Solid-State Circuits Letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10949609/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
A Low-Power Fully Dynamic Latched Comparator Using Flexible Oxide TFT Technology
This letter presents a novel low-power, fully dynamic, latched comparator using only n-type, single-gate amorphous-indium-gallium-zinc-oxide thin-film transistors (a-IGZO TFTs) on a $27~\mu $ m thick polyimide substrate. This circuit demonstrates a stable performance up to an input signal frequency of 15 kHz with 1-MHz clock. By employing a pseudo-CMOS bootstrapped load, it achieved an output voltage swing of around 90%, an input-referred offset and noise voltages of 28 mV and 14 mV, respectively from measurements. In addition, it can reliably detect a minimum differential input voltage of 50 mV at a $V_{\mathrm { DD}}$ of 4 V, while consuming only $8~\mu $ W power. Therefore, this design is well-suited in biomedical wearable devices which typically needs low-power.