基于逆变器的采样前端在50 ghz输入下实现>46-dB SFDR

IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Solid-State Circuits Letters Pub Date : 2025-03-18 DOI:10.1109/LSSC.2025.3552520

Zehang Wu;Chi-Hang Chan;Yan Zhu;Rui P. Martins;Minglei Zhang

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引用次数: 0

摘要

本文介绍了一种用于时间交错adc的32gs /s的分层采样前端（SFE），具有高线性度和高能效，并具有基于逆变器拓扑的固有嵌入式增益。P/N比配置扩展了其适用的输入共模电压范围。有源和无源扩展都提高了由核心器件电压提供的SFE的带宽。此外，改进的双路自举开关提高了采样带宽和8gs /s的线性度。基于逆变器的SFE采用28纳米CMOS工艺制造，在0.95 v电源消耗49.4 mW的情况下实现30 ghz带宽。在50 ghz输入时，测量到的无杂散动态范围（SFDR）和信噪比（SNDR）分别为46.9 dB和36.1 dB。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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An Inverter-Based Sampling Front-End Achieving >46-dB SFDR at 50-GHz Input

This letter presents a 32-GS/s per-way hierarchical sampling front-end (SFE) for time-interleaved ADCs, featuring both high linearity and energy efficiency with inherent embedded gain from an inverter-based topology. The P/N ratio configuration extends its applicable input common-mode voltage range. Both active and passive extensions improve the bandwidth of the SFE supplied by a core-device voltage. Furthermore, an improved dual-path bootstrapped switch enhances the sampling bandwidth and linearity at 8 GS/s. Fabricated in a 28-nm CMOS process, the inverter-based SFE achieves 30-GHz bandwidth while consuming 49.4 mW from a 0.95-V supply. The measured spurious free dynamic range (SFDR) and signal-to-noise and -distortion ratio (SNDR) at 50-GHz input are 46.9 dB and 36.1 dB, respectively.

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来源期刊

IEEE Solid-State Circuits Letters Engineering-Electrical and Electronic Engineering

CiteScore

4.30

自引率

3.70%

发文量