Two 7–13-GHz GaAs-SiGe Four–Channel Beamforming Chiplets With/Without Metallic Interlayer Shields

IF 2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Solid-State Circuits Letters Pub Date : 2025-03-27 DOI:10.1109/LSSC.2025.3573757

Nengxu Zhu;Yiting Zhang;Genyin Ma;Fanyi Meng

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引用次数: 0

Abstract

This letter presents two 7–13-GHz GaAs-SiGe four-channel beamforming chiplets to minimize the chip area. The chips integrate GaAs-based power amplifiers (PAs) and low-noise amplifiers (LNAs) with silicon-based phase and amplitude control modules using gold bumps. To mitigate coupling between the metal patterns of the heterogeneous chips and avoid interference with beamforming performance, a metallic interlayer shield is introduced at the interface. This shield ensures effective integration and preserves the functionality and performance of both the compound and silicon-based components. The fabricated four-channel 3-D heterogeneous integrated radio-frequency front-end chips, using 0.25-

$\mu $

m GaAs and 0.13-

$\mu $

m SiGe BiCMOS processes, achieve 6-bit amplitude/phase control with 0.5 dB/5.625° resolution with power consumption of 3.6 W (TX) and 1.6 W (RX). The RMS amplitude and phase errors are <0.6> $\mathrm { OP_{1dB}}$ and −1.5-dBm RX IP1dB, with a compact total area of

$4.1\times 3.05$

mm2.

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两种带/不带金属层间屏蔽的7 - 13 ghz GaAs-SiGe四通道波束形成芯片

这封信提出了两个7 - 13 ghz GaAs-SiGe四通道波束成形小芯片，以最大限度地减少芯片面积。该芯片将基于砷化镓的功率放大器（PAs）和低噪声放大器（LNAs）与使用金凸起的硅基相位和幅度控制模块集成在一起。为了减轻非均质芯片金属图案之间的耦合，避免对波束形成性能的干扰，在接口处引入了金属层间屏蔽。这种屏蔽确保了有效的集成，并保留了化合物和硅基组件的功能和性能。该四通道三维异构集成射频前端芯片采用0.25- $\mu $ m GaAs和0.13- $\mu $ m SiGe BiCMOS工艺，实现了6位幅度/相位控制，分辨率为0.5 dB/5.625°，功耗为3.6 W （TX）和1.6 W （RX）。RMS幅值和相位误差分别为$\ mathm {OP_{1dB}}$和- 1.5 dbm RX IP1dB，总面积为$4.1\ × 3.05$ mm2。

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来源期刊

IEEE Solid-State Circuits Letters Engineering-Electrical and Electronic Engineering

CiteScore

4.30

自引率

3.70%

发文量