A 14 nm MRAM-Based Multi-bit Analog In-Memory Computing With Process-Variation Calibration for 72 Macros-Based Accelerator

Abstract

This letter presents an analog in-memory computing (IMC) macro utilizing 14 nm MRAM technology. To facilitate energy-efficient high-throughput multiply accumulate (MAC) operations, a multi-bit weight is introduced using stacked magnetic tunnel junction architecture and an analog bit-parallel MAC (ABP-MAC) scheme is proposed. This approach delivers 3.3 times better TOPS/mm2 than the state-of-the-art MRAM-based IMC macro. Additionally, a comprehensive calibration technique significantly improves computational accuracy across 72 IMC macros. The proposed IMC macro achieves 18.29 TOPS/mm2 and 340.8 TOPS/W with 1-bit normalization and classification accuracy of 90.2% with the Google speech commands dataset.