S2D-CIM: SRAM-Based Systolic Digital Compute-in-Memory Framework With Domino Data Path Supporting Flexible Vector Operation and 2-D Weight Update

Abstract

In this letter, we propose an SRAM-based systolic digital compute-in-memory (S2D-CIM) framework which enables flexible input dataflow and mapping strategy to enhance the effective energy efficiency (EE), area efficiency, and writing bandwidth for practical CIM with innovations: 1) multistage domino data path (DDP); 2) a configurable asynchronous timing scheme; and 3) a 2-D burst writing scheme. The proposed S2D-CIM is fabricated using TSMC 22-nm technology and achieves 9.19 and 24.4 TOPS/W peak EE in systolic mode and broadcast mode, respectively, at full precision of 8-bit input, 8-bit weight, and 21-bit output. Compared with state of the arts, it achieves $1.67\times $ effective EE improvement. Thanks to reusing introduced DDP, fast 2-D weight update is realized and gains 1.187 Tb/s writing bandwidth, which is $14.3\times $ better than that of normal SRAM macro with the same capacity.