S2D-CIM: SRAM-Based Systolic Digital Compute-in-Memory Framework With Domino Data Path Supporting Flexible Vector Operation and 2-D Weight Update

IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Solid-State Circuits Letters Pub Date : 2024-09-19 DOI:10.1109/LSSC.2024.3463697

Meng Wu;Wenjie Ren;Peiyu Chen;Wentao Zhao;Tianyu Jia;Le Ye

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引用次数: 0

Abstract

In this letter, we propose an SRAM-based systolic digital compute-in-memory (S2D-CIM) framework which enables flexible input dataflow and mapping strategy to enhance the effective energy efficiency (EE), area efficiency, and writing bandwidth for practical CIM with innovations: 1) multistage domino data path (DDP); 2) a configurable asynchronous timing scheme; and 3) a 2-D burst writing scheme. The proposed S2D-CIM is fabricated using TSMC 22-nm technology and achieves 9.19 and 24.4 TOPS/W peak EE in systolic mode and broadcast mode, respectively, at full precision of 8-bit input, 8-bit weight, and 21-bit output. Compared with state of the arts, it achieves

$1.67\times $

effective EE improvement. Thanks to reusing introduced DDP, fast 2-D weight update is realized and gains 1.187 Tb/s writing bandwidth, which is

$14.3\times $

better than that of normal SRAM macro with the same capacity.

查看原文本刊更多论文

S2D-CIM：基于 SRAM 的收缩式内存数字计算框架，采用多米诺数据路径，支持灵活的矢量操作和二维权重更新

在这封信中，我们提出了一种基于 SRAM 的收缩式数字内存计算（S2D-CIM）框架，该框架支持灵活的输入数据流和映射策略，通过创新提高了实用 CIM 的有效能效（EE）、面积效率和写入带宽：1) 多级多米诺数据路径 (DDP)；2) 可配置异步定时方案；3) 2-D 突发写入方案。所提出的 S2D-CIM 采用台积电 22 纳米技术制造，在 8 位输入、8 位加权和 21 位输出的全精度条件下，在收缩模式和广播模式下分别实现了 9.19 和 24.4 TOPS/W 峰值 EE。与现有技术相比，它实现了 1.67 美元/次的有效 EE 改进。由于重复使用了引入的 DDP，实现了快速 2-D 权重更新，并获得了 1.187 Tb/s 的写带宽，与相同容量的普通 SRAM 宏相比，提高了 14.3 倍。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Solid-State Circuits Letters Engineering-Electrical and Electronic Engineering

CiteScore

4.30

自引率

3.70%

发文量