具有近 CIM 模拟存储器的 44.3 TOPS/W SRAM 存贮器计算功能，可激活无 DAC/ADC 操作

IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Solid-State Circuits Letters Pub Date : 2024-06-24 DOI:10.1109/LSSC.2024.3418099

Peiyu Chen;Meng Wu;Wentao Zhao;Yufei Ma;Tianyu Jia;Le Ye

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引用次数: 0

摘要

在这封信中，我们介绍了一种模拟内存计算 (CIM) 宏设计，它结合了近 CIM 模拟存储器和非线性激活单元 (NAU)，以缓解 DAC/ADC 的功率瓶颈。全差分模拟存储器采用开关电容存储电路设计。激活功能（如整流线性单元）也在 NAU 的模拟域中执行。CIM 宏采用台积电 55 纳米技术制造，峰值宏级能效为 44.3 TOPS/W，模拟输入和输出的系统能效为 27.7 TOPS/W，权重为 4 位。与 DAC/ADC 解决方案相比，近 CIM 模拟存储器和 NAU 解决方案的能耗降低了 76.0%，能效提高了 1.34 美元至 2.37 美元。

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A 44.3 TOPS/W SRAM Compute-in-Memory With Near-CIM Analog Memory and Activation for DAC/ADC-Less Operations

In this letter, we present an analog compute-in-memory (CIM) macro design which incorporates near-CIM analog memory and nonlinearity activation unit (NAU) to alleviate the DAC/ADC power bottleneck. Fully differential analog memory is designed with switched capacitor storage circuits. Activation function, e.g., rectified linear unit, is also performed in analog domain in NAU. The CIM macro is fabricated using TSMC 55-nm technology, with a peak macro-level efficiency of 44.3 TOPS/W and a system energy efficiency of 27.7 TOPS/W for analog input and output with 4-bit weight. The near-CIM analog memory and NAU solution brings 76.0% energy reduction compared with DAC/ADC solution, which contributes

$1.34\times $

$2.37\times $

energy efficiency improvement.

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来源期刊

IEEE Solid-State Circuits Letters Engineering-Electrical and Electronic Engineering

CiteScore

4.30

自引率

3.70%

发文量