在 4 纳米工艺中实现 60 Mbp/s 的基于 STR 的 PVT 容限 TRNG 及其数学建模性能分析

IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Solid-State Circuits Letters Pub Date : 2024-06-26 DOI:10.1109/LSSC.2024.3419722

Jieun Park;Yong Ki Lee;Karpinskyy Bohdan;Yunhyeok Choi;Jonghoon Shin;Hyo-Gyuem Rhew;Jongshin Shin

{"title":"在 4 纳米工艺中实现 60 Mbp/s 的基于 STR 的 PVT 容限 TRNG 及其数学建模性能分析","authors":"Jieun Park;Yong Ki Lee;Karpinskyy Bohdan;Yunhyeok Choi;Jonghoon Shin;Hyo-Gyuem Rhew;Jongshin Shin","doi":"10.1109/LSSC.2024.3419722","DOIUrl":null,"url":null,"abstract":"This letter presents a high-performance true random number generator (TRNG) based on self-timed ring (STR), showing robust tolerance to PVT variations. The evaluations were performed over 320 chips (64 chips per process corner of nn, ff, ss, sf, and fs) across three voltages (0.75 V, 0.75 V±10%) and three temperatures (\n<inline-formula> <tex-math>$- 40~^{\\circ }$ </tex-math></inline-formula>\nC, \n<inline-formula> <tex-math>$25~^{\\circ }$ </tex-math></inline-formula>\nC, and \n<inline-formula> <tex-math>$150~^{\\circ }$ </tex-math></inline-formula>\nC). All 320 test chips demonstrated stable random generation at 60 Mb/s over all the test combinations without a single failure. The verification utilized a TRNG BIST, ensuring a minimum of 0.5 min-entropy per bit. Moreover, a mathematical model for the proposed TRNG is developed to derive the throughput and the entropy of the random output.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.2000,"publicationDate":"2024-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A PVT-Tolerant STR-Based TRNG in 4-nm Achieving 60 Mbp/s and Its Performance Analysis via Mathematical Modeling\",\"authors\":\"Jieun Park;Yong Ki Lee;Karpinskyy Bohdan;Yunhyeok Choi;Jonghoon Shin;Hyo-Gyuem Rhew;Jongshin Shin\",\"doi\":\"10.1109/LSSC.2024.3419722\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This letter presents a high-performance true random number generator (TRNG) based on self-timed ring (STR), showing robust tolerance to PVT variations. The evaluations were performed over 320 chips (64 chips per process corner of nn, ff, ss, sf, and fs) across three voltages (0.75 V, 0.75 V±10%) and three temperatures (\\n<inline-formula> <tex-math>$- 40~^{\\\\circ }$ </tex-math></inline-formula>\\nC, \\n<inline-formula> <tex-math>$25~^{\\\\circ }$ </tex-math></inline-formula>\\nC, and \\n<inline-formula> <tex-math>$150~^{\\\\circ }$ </tex-math></inline-formula>\\nC). All 320 test chips demonstrated stable random generation at 60 Mb/s over all the test combinations without a single failure. The verification utilized a TRNG BIST, ensuring a minimum of 0.5 min-entropy per bit. Moreover, a mathematical model for the proposed TRNG is developed to derive the throughput and the entropy of the random output.\",\"PeriodicalId\":13032,\"journal\":{\"name\":\"IEEE Solid-State Circuits Letters\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":2.2000,\"publicationDate\":\"2024-06-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Solid-State Circuits Letters\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10572268/\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Solid-State Circuits Letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10572268/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}

引用次数: 0

摘要

这封信介绍了一种基于自定时环（STR）的高性能真随机数发生器（TRNG），显示了对 PVT 变化的强大耐受性。在三种电压（0.75 V、0.75 V±10%）和三种温度（$- 40~^{\circ }$ C、$25~^{\circ }$ C 和 $150~^{\circ }$ C）下，对 320 个芯片（nn、ff、ss、ssf 和 fs 的每个工艺角 64 个芯片）进行了评估。在所有测试组合中，所有 320 个测试芯片都以 60 Mb/s 的速度稳定生成随机数据，没有出现任何故障。验证采用了 TRNG BIST，确保了每比特最小 0.5 min-熵。此外，还为拟议的 TRNG 建立了一个数学模型，以推导随机输出的吞吐量和熵。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A PVT-Tolerant STR-Based TRNG in 4-nm Achieving 60 Mbp/s and Its Performance Analysis via Mathematical Modeling

This letter presents a high-performance true random number generator (TRNG) based on self-timed ring (STR), showing robust tolerance to PVT variations. The evaluations were performed over 320 chips (64 chips per process corner of nn, ff, ss, sf, and fs) across three voltages (0.75 V, 0.75 V±10%) and three temperatures (

$- 40~^{\circ }$

$25~^{\circ }$

C, and

$150~^{\circ }$

C). All 320 test chips demonstrated stable random generation at 60 Mb/s over all the test combinations without a single failure. The verification utilized a TRNG BIST, ensuring a minimum of 0.5 min-entropy per bit. Moreover, a mathematical model for the proposed TRNG is developed to derive the throughput and the entropy of the random output.

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来源期刊

IEEE Solid-State Circuits Letters Engineering-Electrical and Electronic Engineering

CiteScore

4.30

自引率

3.70%

发文量