具有共模输入跟踪功能的 7-b 76-mW 40-GS/s 混合电压/时域 ADC

IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Solid-State Circuits Letters Pub Date : 2024-07-18 DOI:10.1109/LSSC.2024.3430851

Amy Whitcombe;Somnath Kundu;Hariprasad Chandrakumar;Abhishek Agrawal;Thomas Brown;Steven Callender;Brent Carlton;Stefano Pellerano

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引用次数: 0

摘要

高速链路需要快速、中等分辨率、低功耗的模数转换器 (ADC)，以最大限度地提高效率。混合电压和时间（V+T）模数转换器可将时域转换的速度优势与传统电压域模数转换器的可靠性结合起来。这封信展示了：1）V+T 架构如何简化时间交错的实现；2）强调了提高 V+T 子 ADC 稳健性的两种方法：a）具有共模输入电压跟踪功能的电压-时间转换器 (VTC)；b）合并的时间-电压转换器和闪存时间-数字转换器。在 0.103 平方毫米的 22 纳米 CMOS 原型中进行了演示，该原型功耗为 76 毫瓦，在 40 GS/s 的 Nyquist 输入条件下可提供 32.3 分贝的 SNDR，FoMw 为 57 fJ/step。

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A 7-b 76-mW 40-GS/s Hybrid Voltage/Time-Domain ADC With Common-Mode Input Tracking

High-speed links require fast, moderate resolution analog-to-digital converters (ADCs) with low power to maximize efficiency. Hybrid voltage and time (V+T) ADCs can combine the speed benefits of time-domain conversion with the reliability of conventional voltage-domain ADCs. This letter demonstrates 1) how the V+T architecture can simplify time interleaving implementation and 2) highlights two methods for improving V+T sub-ADC robustness: a) a voltage-to-time converter (VTC) with common-mode input voltage tracking and b) a merged time-to-voltage and flash time-to-digital converter. This is demonstrated in a 0.103-mm2 22-nm CMOS prototype that consumes 76 mW and gives 32.3-dB SNDR with a Nyquist input at 40 GS/s, for 57-fJ/step FoMw.

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来源期刊

IEEE Solid-State Circuits Letters Engineering-Electrical and Electronic Engineering

CiteScore

4.30

自引率

3.70%

发文量