{"title":"具有异步100/167 Mb/s ASK/FSK全双工通信的栅极驱动器的完全集成电隔离器","authors":"Lucrezia Navarin;Karl Norling;Marco Parenzan;Stefano Ruzzu;Andrea Neviani;Andrea Bevilacqua","doi":"10.1109/LSSC.2025.3611018","DOIUrl":null,"url":null,"abstract":"A fully integrated galvanic isolator for gate drivers that supports high-speed, asynchronous, full-duplex communication is presented. Data transmission from the microcontroller to the power device is achieved using amplitude-shift keying (ASK) at 100 Mb/s, while simultaneous communication in the opposite direction is implemented using frequency-shift keying (FSK) at 167 Mb/s. A delay-locked loop (DLL)-based FSK demodulator enables robust operation in a completely asynchronous communication scenario. Prototypes were fabricated in a 0.13-<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>m HV CMOS technology, covering an area of 2.2 mm2. The system operates from a low 1.5-V supply with a total power consumption of 8.2 mW. Measured propagation delays are under 8 ns for ASK and below 4 ns for FSK at their respective maximum data rates.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"289-292"},"PeriodicalIF":2.0000,"publicationDate":"2025-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Fully Integrated Galvanic Isolator for Gate Drivers With Asynchronous 100/167 Mb/s ASK/FSK Full-Duplex Communication\",\"authors\":\"Lucrezia Navarin;Karl Norling;Marco Parenzan;Stefano Ruzzu;Andrea Neviani;Andrea Bevilacqua\",\"doi\":\"10.1109/LSSC.2025.3611018\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A fully integrated galvanic isolator for gate drivers that supports high-speed, asynchronous, full-duplex communication is presented. Data transmission from the microcontroller to the power device is achieved using amplitude-shift keying (ASK) at 100 Mb/s, while simultaneous communication in the opposite direction is implemented using frequency-shift keying (FSK) at 167 Mb/s. A delay-locked loop (DLL)-based FSK demodulator enables robust operation in a completely asynchronous communication scenario. Prototypes were fabricated in a 0.13-<inline-formula> <tex-math>$\\\\mu $ </tex-math></inline-formula>m HV CMOS technology, covering an area of 2.2 mm2. The system operates from a low 1.5-V supply with a total power consumption of 8.2 mW. Measured propagation delays are under 8 ns for ASK and below 4 ns for FSK at their respective maximum data rates.\",\"PeriodicalId\":13032,\"journal\":{\"name\":\"IEEE Solid-State Circuits Letters\",\"volume\":\"8 \",\"pages\":\"289-292\"},\"PeriodicalIF\":2.0000,\"publicationDate\":\"2025-09-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Solid-State Circuits Letters\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/11168847/\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Solid-State Circuits Letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/11168847/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
A Fully Integrated Galvanic Isolator for Gate Drivers With Asynchronous 100/167 Mb/s ASK/FSK Full-Duplex Communication
A fully integrated galvanic isolator for gate drivers that supports high-speed, asynchronous, full-duplex communication is presented. Data transmission from the microcontroller to the power device is achieved using amplitude-shift keying (ASK) at 100 Mb/s, while simultaneous communication in the opposite direction is implemented using frequency-shift keying (FSK) at 167 Mb/s. A delay-locked loop (DLL)-based FSK demodulator enables robust operation in a completely asynchronous communication scenario. Prototypes were fabricated in a 0.13-$\mu $ m HV CMOS technology, covering an area of 2.2 mm2. The system operates from a low 1.5-V supply with a total power consumption of 8.2 mW. Measured propagation delays are under 8 ns for ASK and below 4 ns for FSK at their respective maximum data rates.