Ronald Wijermars;Yi-Han Ou-Yang;Sijun Du;Dante G. Muratore
{"title":"A 40.68-MHz, 200-ns-Settling Active Rectifier for mm-Sized Implants","authors":"Ronald Wijermars;Yi-Han Ou-Yang;Sijun Du;Dante G. Muratore","doi":"10.1109/LSSC.2025.3611484","DOIUrl":null,"url":null,"abstract":"This letter describes a fast-settling active rectifier for a 40.68 MHz wireless power transfer receiver for implantable applications. Fast-settling and low power are achieved through a novel direct voltage-domain compensation technique. The rectifier maintains high efficiency during load and link variations required for downlink communication. The system was fabricated in 40nm CMOS and achieves a voltage conversion ratio of 93.9% and a simulated power conversion efficiency of 90.1% in a 0.19 mm2 area, resulting in a 118 mW/mm2 power density while integrating the resonance and filter capacitors. The worst-case settling of the ON- and OFF-delay compensation in the active rectifier is 200 ns, which is the fastest reported to date.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"305-308"},"PeriodicalIF":2.0000,"publicationDate":"2025-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Solid-State Circuits Letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/11172323/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
This letter describes a fast-settling active rectifier for a 40.68 MHz wireless power transfer receiver for implantable applications. Fast-settling and low power are achieved through a novel direct voltage-domain compensation technique. The rectifier maintains high efficiency during load and link variations required for downlink communication. The system was fabricated in 40nm CMOS and achieves a voltage conversion ratio of 93.9% and a simulated power conversion efficiency of 90.1% in a 0.19 mm2 area, resulting in a 118 mW/mm2 power density while integrating the resonance and filter capacitors. The worst-case settling of the ON- and OFF-delay compensation in the active rectifier is 200 ns, which is the fastest reported to date.