A 65-nm Delta-Sigma ADC-Based VDD-Variation-Tolerant Power-Side-Channel-Attack Sensor

IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Solid-State Circuits Letters Pub Date : 2025-01-08 DOI:10.1109/LSSC.2025.3527153

Shota Konno;Zachary J. Ellis;Anupam Golder;Sigang Ryu;Daniel Dinu;Avinash Varna;Sanu Mathew;Arijit Raychowdhury

引用次数: 0

Abstract

This letter describes a delta-sigma ADC-based power-side-channel-attack sensor. Use of 64 sampling capacitors allows the use of over-sampling architecture even with a decoupling capacitor connected to the power supply. The LDO with low-leakage S/H is used as a driver for the integrator’s amplifier to minimize the offset error. A differential conversion method utilizing dual-integrate capacitors (CAPs) provides signal processing to compensate for drift due to supply voltage (VDD) variations. The prototype sensor chip fabricated in 65-nm CMOS has a worst-case detection accuracy of 98.7%, including VDD variations, for an insertion resistance >

${=}0.25~\Omega $

and a power consumption of

$50~\mu $

W at 1.0-V operation.

查看原文本刊更多论文

一种65纳米Delta-Sigma adc型vdd容差功率侧信道攻击传感器

这封信描述了一种基于delta-sigma adc的功率侧信道攻击传感器。使用64个采样电容允许使用过采样架构，即使与电源连接的去耦电容。具有低漏S/H的LDO用作积分器放大器的驱动器，以最小化偏移误差。差分转换方法利用双积分电容器（CAPs）提供信号处理，以补偿由电源电压（VDD）变化引起的漂移。该传感器原型芯片采用65纳米CMOS工艺，最坏情况检测精度为98.7%, including VDD variations, for an insertion resistance > ${=}0.25~\Omega $ and a power consumption of $50~\mu $ W at 1.0-V operation.

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

IEEE Solid-State Circuits Letters Engineering-Electrical and Electronic Engineering

CiteScore

4.30

自引率

3.70%

发文量