具有1/4 dtc范围缩减技术的低抖动分数n lc -锁相环

IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Solid-State Circuits Letters Pub Date : 2025-01-10 DOI:10.1109/LSSC.2025.3528005

Gaofeng Jin;Fei Feng;Yan Chen;Hanli Liu;Xiang Gao

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引用次数: 0

摘要

提出了一种基于分数n LC振荡器的锁相环（PLL），该锁相环具有1/4量化噪声（QN）降程技术。简单的开环延迟单元用于产生4相时钟，并将QN降低4倍，同时对4相的不匹配进行校准并由单个DTC覆盖。该锁相环采用40nm CMOS工艺设计，实现了159fs的rms抖动，功耗为2.6 mw， FoM为- 251.8 db。

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A Low-Jitter Fractional-N LC-PLL With a 1/4 DTC-Range-Reduction Technique

A fractional-N LC oscillator-based phase-locked loop (PLL) with a 1/4 quantization noise (QN) range reduction technique is proposed. Simple open-loop delay cells are used to generate 4-phase clocks and reduce the QN by a factor of 4 while the mismatches of the four phases are calibrated and covered by a single DTC. Designed in 40-nm CMOS process, the proposed PLL achieves 159-fs RMS-jitter with 2.6-mW power consumption, leading to –251.8-dB FoM.

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来源期刊

IEEE Solid-State Circuits Letters Engineering-Electrical and Electronic Engineering

CiteScore

4.30

自引率

3.70%

发文量