A 2.6-GS/s 8-bit Time-Interleaved ADC With Fully Dynamic Current Integrating Sampler

Abstract

This letter presents an 8-bit 2.6-GS/s 8-way time-interleaved (TI) analog-to-digital converter (ADC) in 65-nm CMOS. The proposed dynamic current integrating sampler (DCIS) implements the functionality of input buffer and anti-aliasing filter, and eliminates the memory effect caused by parasitic capacitance. It breaks through the limitations of conventional CIS in terms of power consumption, output swing, and bandwidth. A global master sampling network with charge sharing is adopted to alleviate the impact of timing skew. The measured results show that the TI-ADC achieves an SFDR of 50.01 dB and SNDR of 41.29 dB with Nyquist input, respectively. The total power consumption is 28.88 mW, which corresponds to a Walden figure of merit of 117.2 fJ/conv.-step.