A Sub-THz Harmonic Recycling Single-Stage Frequency Quadrupler in CMOS 28-nm Technology

Abstract

A single-stage frequency quadrupler operating in the 199–219-GHz frequency range is presented. The quadrupler utilizes a second harmonic trap and recycles the trapped power to generate additional power toward the desired fourth harmonic. The quadrupler has a peak power of −2.54 dBm while consuming 54 mW, resulting in a maximum efficiency $\eta _{\mathrm {MAX}}=1.03\%$ . The circuit occupies an area of $370~\mu $ m $\times $ $240~\mu $ m, the smallest footprint among the reported sub-THz frequency quadruplers. An on-chip LC oscillator and a tuned buffer provide the input signal to the quadrupler, constituting a fully integrated system.