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2015 China Semiconductor Technology International Conference最新文献

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Investigation of surface plasmon enhanced organic light emitting diode by numerical analysis 表面等离子体增强有机发光二极管的数值分析研究
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153469
Wan-Jung Yang, C. Hu, Tomi T. T. Li
{"title":"Investigation of surface plasmon enhanced organic light emitting diode by numerical analysis","authors":"Wan-Jung Yang, C. Hu, Tomi T. T. Li","doi":"10.1109/CSTIC.2015.7153469","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153469","url":null,"abstract":"In this paper, a numerical analysis that approaches to model localized surface plasmon (LSP) leading to enhance lighting intensity in organic light emitting diode (OLED) is reported. LSP was applied in enhancing signal of Raman Spectroscopy, absorptivity of solar cell and lighting intensity of light emitting diode (LED), etc. It is commonly manufactured from metal nanoparticles, and the enhancement of light emitting is dependent on the size, period and geometry of these nanoparticles. We build a simulation model to obtain optimum parameters which provide a way to assist the research of OLED.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122949955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Wafer edge overlay control for 28 nm and beyond technology node 28纳米及以上技术节点的晶圆边缘覆盖控制
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153358
Rui Wang, Yuntao Jiang, Guogui Deng, Bin Xing, Chang Liu, Qiang Wu
{"title":"Wafer edge overlay control for 28 nm and beyond technology node","authors":"Rui Wang, Yuntao Jiang, Guogui Deng, Bin Xing, Chang Liu, Qiang Wu","doi":"10.1109/CSTIC.2015.7153358","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153358","url":null,"abstract":"Advanced semiconductor industry requires chips with higher integration density and smaller critical dimensions, which means the overlay has to be shrunk in proportion. According to the International Technology Roadmap for Semiconductors (ITRS), the overlay requirement for 28 nm is 5.4 nm in 3-sigma. Generally speaking, this overlay requirement can be met with the current state-of-the-art exposure tools. Recently, researchers specifically look at the edge die overlay within a typical 140 mm to 147 mm range in wafer radius. The result is much worse than that of full map overlay. In this paper, multiple root causes of the bad edge overlay are discussed in detail. Among these contributors, un-optimized overlay sampling plan, high order alignment, chuck edge cleanliness, alignment strategy optimization and inappropriate baseliner sub-recipe generation method play major roles. In order to minimize the impact from these overlay contribution factors, corresponding solutions have been explored. Our conclusion is that the edge overlay can be minimized to some extent, while it's very challenging to bring the wafer edge overlay performance to the level of full map overlay.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122826968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
PMMA removal selectivity to PS using dry etch approach for sub-10nm node applications 在10nm以下的节点应用中，使用干蚀刻方法去除PMMA对PS的选择性
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153384
A. Sarrazin, P. Pimenta-Barros, N. Possémé, S. Barnola, A. Gharbi, M. Argoud, R. Tiron, C. Cardinaud
{"title":"PMMA removal selectivity to PS using dry etch approach for sub-10nm node applications","authors":"A. Sarrazin, P. Pimenta-Barros, N. Possémé, S. Barnola, A. Gharbi, M. Argoud, R. Tiron, C. Cardinaud","doi":"10.1109/CSTIC.2015.7153384","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153384","url":null,"abstract":"Directed Self-Assembly (DSA) of Block Copolymers (BCP) is one of the most promising alternative lithography techniques for sub-10 nm nodes. In this paper, we propose to study PMMA removal selectively to PS by plasma etching. This challenge requires a good selectivity between both polymers. Our best chemistries developed on blanket wafers have been tested on cylindrical and lamellar patterned wafers.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128703368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Hard mask profile and loading issue study in SADP process SADP过程中硬掩模轮廓和加载问题的研究
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153372
Ermin Chong, YiZheng Zhu, C. Yi, Xianguo Dong, L. Zhang, Quanbo Li, Jun Huang, Yu Zhang
{"title":"Hard mask profile and loading issue study in SADP process","authors":"Ermin Chong, YiZheng Zhu, C. Yi, Xianguo Dong, L. Zhang, Quanbo Li, Jun Huang, Yu Zhang","doi":"10.1109/CSTIC.2015.7153372","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153372","url":null,"abstract":"Double Patterning (DP) technique is developed and applied to 45nm technology node and beyond by improving litho equipment and process windows. In addition in the 14/16nm node, the planar device is replaced by 3D FINFET architecture for device performance improvement; the SADP (self-align double patterning) technique is developed for FIN formation with focus on the smaller CD and LER (line edge roughness) evolution. The challenges during process development are FIN profile loading, core film profile tuning and others. In this paper, the authors introduce FIN formation and the main challenges during process development.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123812326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
40nm offset spacer process optimization to improve device stability and mismatch 40nm偏置间隔片工艺优化，提高器件稳定性和失配
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153326
Chen Ji, Zhibin He, Xubin Jing, Wei Liu, W. Chang, Yu Zhang, A. Pang
{"title":"40nm offset spacer process optimization to improve device stability and mismatch","authors":"Chen Ji, Zhibin He, Xubin Jing, Wei Liu, W. Chang, Yu Zhang, A. Pang","doi":"10.1109/CSTIC.2015.7153326","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153326","url":null,"abstract":"Continuously shrinking of device CD imposes lots of demanding requirements on wafer manufacturing. In FEOL of wafer processing, device performance will be seriously impacted by the structure including AA/POLY/SPACER. Offset Spacer post Gate POLY increases LDD extension and improves short channel effect, which is a very important factor for good final device performance. This paper focuses on risk assessment for current HLMC 40nm offset spacer process. By changing offset spacer film and optimizing LDD/PKT implant are shown to improve SRAM device mismatch and Vccmin yield performance.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123367848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The approaching of capacitance-voltage measurement toward real-world nano-device 实际纳米器件电容电压测量方法的探讨
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153454
Li-Lung Lai, Nan Li, Oscar Zhang
{"title":"The approaching of capacitance-voltage measurement toward real-world nano-device","authors":"Li-Lung Lai, Nan Li, Oscar Zhang","doi":"10.1109/CSTIC.2015.7153454","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153454","url":null,"abstract":"Owing to the advancing development of electrical technique in analytical laboratory, we already have capability to measure tiny capacitance, down to 100aF, in Nano-dimension, down to 20nm, of the real-world Nano-device using Nanoprobing in SEM or AFM instead of traditional Micro-probing in OM instrument become real of the claim. The mechanism, operation and application are described and discussed in the content.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121784842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
40Nm contact related process optimization for defect reduction 40Nm接触相关工艺优化，以减少缺陷
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153320
Zhibin He, Xubin Jing, Jian Cao, Yuming Qiu, Junhua Yan, Jun Zhou, A. Pang
{"title":"40Nm contact related process optimization for defect reduction","authors":"Zhibin He, Xubin Jing, Jian Cao, Yuming Qiu, Junhua Yan, Jun Zhou, A. Pang","doi":"10.1109/CSTIC.2015.7153320","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153320","url":null,"abstract":"Ni (Nickel) piping, Contact openness, and W (Tungsten) recess are three major defects encountered in 40nm Contact related process development. In this paper, PAI (Pre- Amorphous Implantation) and Ni capping layer were optimized for Ni piping reduction. Contact etch process window was enlarged to eliminate Contact openness. The specific PMOS-localized defect phenomenon was studied. High ILD (Interlayer Dielectric) CMP oxide loss was found responsible to cause poor post-CMP uniformity, which was the main contributor to W recess defect thereafter. Finally, we had obtained an effective ILD thickness and uniformity control in CMP and thus, solving W recess defect.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121731848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A study of self-aligned contact etch of NOR flash NOR闪光自对准接触刻蚀的研究
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153388
Erhu Zheng, Yi-ying Zhang, H. Zhang
{"title":"A study of self-aligned contact etch of NOR flash","authors":"Erhu Zheng, Yi-ying Zhang, H. Zhang","doi":"10.1109/CSTIC.2015.7153388","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153388","url":null,"abstract":"The self-aligned contact (SAC) scheme has been imperative for NOR flash memory technology with the aggressively scaled drain space. The challenges mainly come from its high aspect ratio and the multiple issues to solve such as nitride loss loading between hole and trench, bottom profile and narrow process window. In this course, we investigated two integration schemes, the traditional SAC scheme is to simultaneously form the hole and the trench, followed by tungsten gap-fill, the reversed SAC scheme, is to only form the hole first, followed by nitride deposition. In both schemes, we examined the impact of various etch parameters on the high aspect ratio SAC etch process, including temperature, power, chemistry ratio and pulsing function. Finally we demonstrated the SAC could be successfully fabricated without any side effect.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130073816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
ESD gated diode SPICE compact model ESD门控二极管SPICE紧凑型
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153319
Z. Gan, An Zhang, W. Wong, Lifei Zhang, Ye Haohua, C. Tseng
{"title":"ESD gated diode SPICE compact model","authors":"Z. Gan, An Zhang, W. Wong, Lifei Zhang, Ye Haohua, C. Tseng","doi":"10.1109/CSTIC.2015.7153319","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153319","url":null,"abstract":"A physics-based new gated diode SPICE compact model is provided considering the following two effects: (1) the leakage current under reverse bias of gated diode caused by the gate/diffusion overlap tunneling current; (2) the substrate conductivity modulation associated with high injection of carriers due to mobility saturation during high current transmission line pulse (TLP). The new SPICE model matches the silicon data under both ESD TLP and normal DC forward/reverse bias very well. The model is scalable in terms of finger width and number.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130129140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Numerical analysis for thermal field of susceptor in MOCVD reactor MOCVD反应器中感受器热场数值分析
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153470
Kuo-hung Ho, C. Hu, Tomi T. T. Li
{"title":"Numerical analysis for thermal field of susceptor in MOCVD reactor","authors":"Kuo-hung Ho, C. Hu, Tomi T. T. Li","doi":"10.1109/CSTIC.2015.7153470","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153470","url":null,"abstract":"A MOCVD process requires not only high heating efficiency, but also good temperature uniformity on susceptor surface. The most common material of susceptor is graphite, but the heating lifetime is very short. Instead, this work uses the SiC as susceptor material. It enhances both the lifetime and thermal conductivity. In the meantime, we also change the shape and structure of susceptor to improve the temperature uniformity on the surface. In addition, the gas flow rate and wall temperature will affect the temperature uniformity thus the analysis of thermal flow field is also included. By using above methods, the temperature uniformity of susceptor can improve about 45%.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133961601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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