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2015 China Semiconductor Technology International Conference最新文献

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A wide input voltage range, output-capacitorless linear voltage regulator in 0.25UM BCD process 0.25UM BCD工艺中宽输入电压范围、无输出电容线性稳压器
2015 China Semiconductor Technology International Conference Pub Date : 2015-07-13 DOI: 10.1109/CSTIC.2015.7153481
Danhui Wang, Yuanfu Zhao, S. Yue
{"title":"A wide input voltage range, output-capacitorless linear voltage regulator in 0.25UM BCD process","authors":"Danhui Wang, Yuanfu Zhao, S. Yue","doi":"10.1109/CSTIC.2015.7153481","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153481","url":null,"abstract":"Linear voltage regulators are widely used in electronic systems for low noise and precise output voltage. This paper presents an output-capacitorless linear voltage regulator with 5.5V~40V input voltage, 5V output voltage and 100mA load current. The damping-factor-control (DFC) frequency compensation has effectively enhanced the loop stability. A high to low circuit is presented to supply power for the low working voltage bandgap. Finally, the load regulation is 75uV/mA @ VIN=40V; line regulation is 0.0019%; quiescent current is 130μA @VIN=5.5V and 600μA @VIN=40V. The proposed regulator also has fine load transient response.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131302600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Evaluation of Mask Fidelity using automated edge placement error measurement with CD-SEM images 利用CD-SEM图像的自动边缘放置误差测量来评估掩膜保真度
2015 China Semiconductor Technology International Conference Pub Date : 2015-07-13 DOI: 10.1109/CSTIC.2015.7153359
Zubiao Fu, Shijian Zhang, Yi Huang, Yi-Shih Lin, Lanyan Shi, Cong Zhang, Yaoming Shi, Yiping Xu
{"title":"Evaluation of Mask Fidelity using automated edge placement error measurement with CD-SEM images","authors":"Zubiao Fu, Shijian Zhang, Yi Huang, Yi-Shih Lin, Lanyan Shi, Cong Zhang, Yaoming Shi, Yiping Xu","doi":"10.1109/CSTIC.2015.7153359","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153359","url":null,"abstract":"Mask Fidelity plays a vital role in the lithography process of cutting-edge IC fabrication. The Fidelity of Mask is fundamental to the final performance of the lithography process in production. A contour is extracted from the CD-SEM image of the corresponding fabricated mask under evaluation with at best one pixel resolution. This contour is then used to compare with the intended layout from the mask design file (GDS file). The edge placement error (EPE) between extracted CD-SEM image contour and design layout is then measured and analyzed. An accurate measurement of edge placement error with sub-pixel resolution is very crucial to evaluate the quality of the fabricated mask, therefore, the final produced pattern on wafer after the lithography process in production.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121248643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Discussion on overlay control for 2X nm technology node and beyond 2X nm及以上技术节点的覆盖控制探讨
2015 China Semiconductor Technology International Conference Pub Date : 2015-07-13 DOI: 10.1109/CSTIC.2015.7153357
Yuntao Jiang, Guogui Deng, Bin Xing, Gaorong Li, Jinan Hao, Qiang Wu
{"title":"Discussion on overlay control for 2X nm technology node and beyond","authors":"Yuntao Jiang, Guogui Deng, Bin Xing, Gaorong Li, Jinan Hao, Qiang Wu","doi":"10.1109/CSTIC.2015.7153357","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153357","url":null,"abstract":"Moving to the 28 nm technology node and beyond, contact to poly overlay requirement becomes more and more stringent in order to achieve manufacturable static random access memory (SRAM) yield. Typically, a 6 nm or even better on product overlay (OPO) performance have to be met [1]. With the inception of metal gate process and the associated chemical mechanical planarization (CMP) process, it's more difficult to guarantee desired overlay performance. In this paper, potential source of overlay was analyzed and broken down according to our tool and process condition. Among quite a few overlay contributors, mask registration is playing a more and more important role. Besides mask, the upstream process impact on alignment mark was studied in this paper. In addition, reticle heating effect was studied and the compensation of it was assessed by simulation. Finally, we have also explored the capability of high order process control and metrology sampling optimization. If the overlay source can be properly broken down and each contributor can be squeezed to minimum level, overlay performance can fulfill manufacturing requirement.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132496528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
STI gap-fill optimization for advanced nodes 先进节点的STI空隙填充优化
2015 China Semiconductor Technology International Conference Pub Date : 2015-07-13 DOI: 10.1109/CSTIC.2015.7153395
Jun Yang, Yan Yan, Hao Deng, Beichao Zhang
{"title":"STI gap-fill optimization for advanced nodes","authors":"Jun Yang, Yan Yan, Hao Deng, Beichao Zhang","doi":"10.1109/CSTIC.2015.7153395","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153395","url":null,"abstract":"High aspect ratio process (HARP) and siconi process is widely used for STI gap fill in sub-65nm CMOS; it has good gap fill performance to high aspect profile. As IC technology advances to 28 nm and beyond, void free, high throughput and good uniformity STI gap fill has become a significant process challenge. In this work, we optimize AA etch profile and HARP process to improve STI gap fill. Use O3 or H2 plasma treat ISSG (in-situ steam generation) wafer surface to adjust the surface condition before STI cap. The result shows that after O3 plasma treatment HARP STI film has good film thickness uniformity and high film grow rate on ISSG wafer. From TEM cut and top down scan, void free and high throughput STI gap fill process has been achieved.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133406464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Investigation and solution of intermittent GOI failures at 40 nm CMOS devices 40 nm CMOS器件间歇GOI故障的研究与解决
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153406
Ming Zhou
{"title":"Investigation and solution of intermittent GOI failures at 40 nm CMOS devices","authors":"Ming Zhou","doi":"10.1109/CSTIC.2015.7153406","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153406","url":null,"abstract":"Low k (dielectric constant) barrier (SiCN) is one of the most critical dielectric films used in Cu interconnects, and it has great impact on device reliability such as gate oxide integrity (GOI), plasma induced damage (PID), time-dependent dielectric breakdown (TDDB), electromigration (EM) and so on. This work was to investigate an intermittent GOI failure at 40nm CMOS devices, which was caused by low-k Cu barrier film deposition, and develop an improved process to resolve this issue. To understand the GOI failures, surface charge was collected at various process conditions. It was found, however, that the processes with the lowest surface charge and the best charge non-uniformity didn't improve GOI unexpectedly. The GOI issue was resolved instead by optimizing the RF ramp-up setting and inserting a novel enhanced nitride interface (ENI) layer (~30A). Further studies found that the GOI damage was primarily formed during the plasma ignition step and was related to instantaneous plasma non-uniformity. Well controlled plasma ignition and better Cu surface protection were the keys to achieve good GOI performance.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115319482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Via auto retarget application in 28nm technology node 通过在28nm技术节点上的自动重定向应用
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153340
Bin-Jie Jiang, Yu Shi-rui, Dan Wang, Yue-Yu Zhang, Yanpeng Chen, Zhibiao Mao
{"title":"Via auto retarget application in 28nm technology node","authors":"Bin-Jie Jiang, Yu Shi-rui, Dan Wang, Yue-Yu Zhang, Yanpeng Chen, Zhibiao Mao","doi":"10.1109/CSTIC.2015.7153340","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153340","url":null,"abstract":"In 28nm technology node, developing an enough lithographic process window of VIA layer became a major challenge in order to meet the requirements of the connectivity between metal lines. It is widely used to size up VIA in order to enlarge VIA process window if the space between VIA holes and VIA enclosed by metal is big enough. But the traditional retarget method has its own limits as the retarget rule table cannot deal with every complex environment for each VIA hole. In this paper, we studied several issues in the application of CALIBRE auto-retarget function in VIA model-based OPC correction after the traditional retarget treatment. The parameters of the auto-retarget function are optimized based on simulated results and the SEM data of the corresponding VIA holes are collected for DOF verification. The impact of the auto-retarget function on model-based OPC runtime is also evaluated. It is shown in the simulation result that the DOF of certain SRAM patterns can be enlarged as much as to 30nm after applying the auto-retarget function. The silicon data confirms the simulation prediction and that the DOF of the patterns become enough for lithographic process. Meanwhile, auto-retarget has little impact on model-based OPC runtime.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123553502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An optimized and unified system for FPGA power-up validation to minimize post-silicon cycling time 一个优化和统一的系统，FPGA上电验证，以减少硅后循环时间
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153467
Hua Hua, Hongpeng Han
{"title":"An optimized and unified system for FPGA power-up validation to minimize post-silicon cycling time","authors":"Hua Hua, Hongpeng Han","doi":"10.1109/CSTIC.2015.7153467","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153467","url":null,"abstract":"Power-up validation is a critical process in R&D of FPGA, since it will determine if a FPGA can work correctly at the very first step of operation. Power-up validation includes 4 separate blocks. Testing each block one by one couldn't meet today's short time-to market requirement for a new product. In this paper, an optimized and unified system is proposed to perform validation for all power-up items. The validation efficiency was improved by several times comparing to the traditional approach. The experimental results indicate nearly 90% test time can be saved for the power-up validation.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123801580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Technology for polymer-based integrated optical interferometric sensors fabricated by hot-embossing and printing 基于聚合物的热压和印刷集成光学干涉传感器技术
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153476
Yanfen Xiao, M. Hofmann, S. Sherman, Yixiao Wang, H. Zappe
{"title":"Technology for polymer-based integrated optical interferometric sensors fabricated by hot-embossing and printing","authors":"Yanfen Xiao, M. Hofmann, S. Sherman, Yixiao Wang, H. Zappe","doi":"10.1109/CSTIC.2015.7153476","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153476","url":null,"abstract":"Integrated optical Mach-Zehnder interferometers (MZI) may be used as high-sensitivity sensors by taking advantage of the interaction of the waveguide evanescent field with liquids or gases surrounding the sensor. We present here the design and simulation of polymer-based MZIs fabricated using printing technologies. Based on simulations of an integrated MZI system with regard to variations of waveguide cross-section and refractive indices of core and cladding to optimize high sensitivity to external refractive index changes of analytes, waveguides with single mode behavior are fabricated by hot-embossing and ink-jet or flexographic printing technologies. Finally, a hybrid combination of a laser diode with the printed MZI will be shown.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125520472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A pseudo C-2C and CBW hybrid DAC structure used for SAR ADC 一种用于SAR ADC的伪C-2C和CBW混合DAC结构
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153487
Xiaoxu Meng, Wenliang Geng, Yang Cao, Guoxing Wang
{"title":"A pseudo C-2C and CBW hybrid DAC structure used for SAR ADC","authors":"Xiaoxu Meng, Wenliang Geng, Yang Cao, Guoxing Wang","doi":"10.1109/CSTIC.2015.7153487","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153487","url":null,"abstract":"A hybrid DAC structure combined with conventional binary-weighted (CBW) capacitive array and pseudo C-2C capacitive array is proposed in the paper. Causes for nonlinearity of the structure are analyzed, including the effects of parasitics and the deviation of the capacitor adjustment parameter. Analysis of the power consumption and nonlinearity of the hybrid structure is also presented. This structure reduces power consumption by up to 99.1% compared to the conventional one. The linearity degrades with the increase of the number of pseudo C-2C units.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115458214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Innovative ultra fine line substrate with bump for semiconductor package 创新的半导体封装凹凸超细线衬底
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153435
Nozomi Shimoishizka, Takahiro Nakano, K. Hirata
{"title":"Innovative ultra fine line substrate with bump for semiconductor package","authors":"Nozomi Shimoishizka, Takahiro Nakano, K. Hirata","doi":"10.1109/CSTIC.2015.7153435","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153435","url":null,"abstract":"A new ultra fine line substrate with bumps for semiconductor package has been developed in the present study, making it possible to realize 10um pitch line that has been impossible by conventional method. By making bumps and lines at same time through imprinting method, the technology is more suitable for high pin count flip chip bonding substrate. This paper will describe the detail of this ultra fine line substrate with bumps, the fine line imprint process, design rules, and the simulation results of electrical characteristic in DC and high frequency range.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116418195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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