Discussion on overlay control for 2X nm technology node and beyond

Abstract

Moving to the 28 nm technology node and beyond, contact to poly overlay requirement becomes more and more stringent in order to achieve manufacturable static random access memory (SRAM) yield. Typically, a 6 nm or even better on product overlay (OPO) performance have to be met [1]. With the inception of metal gate process and the associated chemical mechanical planarization (CMP) process, it's more difficult to guarantee desired overlay performance. In this paper, potential source of overlay was analyzed and broken down according to our tool and process condition. Among quite a few overlay contributors, mask registration is playing a more and more important role. Besides mask, the upstream process impact on alignment mark was studied in this paper. In addition, reticle heating effect was studied and the compensation of it was assessed by simulation. Finally, we have also explored the capability of high order process control and metrology sampling optimization. If the overlay source can be properly broken down and each contributor can be squeezed to minimum level, overlay performance can fulfill manufacturing requirement.