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2015 China Semiconductor Technology International Conference最新文献

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Etch rate prediction in plasma etching using feed forward Error-Back Propagation neural network model 利用前馈误差-反向传播神经网络模型预测等离子体刻蚀速率
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153456
Ha-Deok Song, Ho-Taek Noh, Dong-Il Kim, Seung-Soo Han
{"title":"Etch rate prediction in plasma etching using feed forward Error-Back Propagation neural network model","authors":"Ha-Deok Song, Ho-Taek Noh, Dong-Il Kim, Seung-Soo Han","doi":"10.1109/CSTIC.2015.7153456","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153456","url":null,"abstract":"In this paper, a Virtual Metrology (VM) model is proposed to predict etch rate which is one of the most important etching profile in etch process. Error Back Propagation (EBP) neural network is used to make the VM for etch rate prediction. Etching process recipe data obtained through the Design of Experiments (DOE) are used to train the VM. The etch rate data are gained through the experiments, and the EBP neural VM model is trained to satisfy the allowable error between predicted etch rate and experimental etch rate. With this trained EBP neural network VM model, it can be possible to predict the etch rate without real experiments.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114701392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Stress measurements on TSVs and BEoL structures with high spatial resolution tsv和BEoL结构的高空间分辨率应力测量
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153465
D. Vogel, E. Auerswald, J. Auersperg, S. Rzepka
{"title":"Stress measurements on TSVs and BEoL structures with high spatial resolution","authors":"D. Vogel, E. Auerswald, J. Auersperg, S. Rzepka","doi":"10.1109/CSTIC.2015.7153465","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153465","url":null,"abstract":"Knowledge and control of local stress development in BEoL stacks and nearby TSVs in advanced 3D integrated devices is a key to their thermo-mechanical reliability. The paper presents a combined simulation / measurement approach to evaluate stresses generated in the result of the TSV and BEoL stack manufacturing and 3D bonding processes. Stress measurement methods of high spatial resolution capability are briefly benchmarked. The application of microRaman and the new FIB based stress release techniques on TSV structures are demonstrated in some detail.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"84 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124292866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Surface modification of hydrogenated amorphous carbon (a-C: H) films prepared by plasma enhanced chemical vapor deposition (PECVD) 等离子体增强化学气相沉积(PECVD)法制备氢化非晶碳(a-C: H)薄膜的表面改性
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153411
Lihong Xiao, Erico Zhou, Huan Liu
{"title":"Surface modification of hydrogenated amorphous carbon (a-C: H) films prepared by plasma enhanced chemical vapor deposition (PECVD)","authors":"Lihong Xiao, Erico Zhou, Huan Liu","doi":"10.1109/CSTIC.2015.7153411","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153411","url":null,"abstract":"Methods to modify the film surface of hydrogenated amorphous carbon (a-C: H) produced by PECVD have been studied. One way is to expose the film to O2-H2 plasma atmosphere, the topographical nature of the resulting surface can be modified substantially due to reaction of O2-H2 plasma with active ions and radicals, and therefore ashed carbon away with thickness decrease. The other way is to immerse films into O3-diluted deionized (DI) water. Free radicals produced at the surface during the PECVD process were quenched by reaction with oxygen and/or water and an oxidized hydrophilic layer was formed at the surface. Therefore, the film thickness, either optically measured by KLA tools or physically demonstrated with TEM images, has proven to be increased, different from that of dry physical etching.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130115531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Method of improving dislocation for SiGe EPI process 改善SiGe EPI工艺位错的方法
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153377
Xiangguo Meng, Quanbo Li, Jun Huang, A. Pang
{"title":"Method of improving dislocation for SiGe EPI process","authors":"Xiangguo Meng, Quanbo Li, Jun Huang, A. Pang","doi":"10.1109/CSTIC.2015.7153377","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153377","url":null,"abstract":"To obtain a defect free and dislocation free during SiGe deposition is the key for improving hole carrier mobility for 40 nm technology node and beyond. This paper presents a methodology to eliminate SiGe dislocation. The key step is to introduce SF6 during Si trench surface treatment after Si trench main etch.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125352535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Mechanism of I–V asymmetry of MIM capacitors based on high-k dielectric 基于高k介电介质的MIM电容器的I-V不对称机理
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153403
W. Lau, D. Q. Yu, X. Wang, H. Wong, Y. Xu
{"title":"Mechanism of I–V asymmetry of MIM capacitors based on high-k dielectric","authors":"W. Lau, D. Q. Yu, X. Wang, H. Wong, Y. Xu","doi":"10.1109/CSTIC.2015.7153403","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153403","url":null,"abstract":"MIM capacitors based on high-k dielectric are used in analog CMOS. They tend to show up an asymmetric I-V characteristics even though they may have an apparently symmetric structure; the same situation occurs for high-k dielectric deposited by CVD or ALD. In this paper, we will propose a physical mechanism for the asymmetric I-V characteristics observed and we will also provide experimental data to support our claim.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115768390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Current status and future prospect for thin film silicon based photovoltaic module manufacturing technology at Hanergy 汉能薄膜硅基光伏组件制造技术现状及未来展望
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153490
Xixiang Xu, Hui Zhao, X. Ru, Xinghong Zhou, Chengjian Hong, Chongyan Lian, C. Peng, M. Qu, Yue Zhang, Yunxue Cao, A. Hu, J. Huang, Jack Xiao, Chuck Hu, Jinyan Zhang, Yuanmin Li
{"title":"Current status and future prospect for thin film silicon based photovoltaic module manufacturing technology at Hanergy","authors":"Xixiang Xu, Hui Zhao, X. Ru, Xinghong Zhou, Chengjian Hong, Chongyan Lian, C. Peng, M. Qu, Yue Zhang, Yunxue Cao, A. Hu, J. Huang, Jack Xiao, Chuck Hu, Jinyan Zhang, Yuanmin Li","doi":"10.1109/CSTIC.2015.7153490","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153490","url":null,"abstract":"We report the recent progress in the development of a-Si/a-SiGe and a-Si/nc-Si multijunction solar cells on the product size substrate of 0.79m2, and heterojunction solar cells on 152.3cm2 n-type silicon wafer at Hanergy. Main experimental results cover three aspects: (a) for a-Si/a-SiGe multijunction solar cells, significant improvement in a-Si/a-SiGe triple junction PV module efficiency by optimizing a-Si and a-SiGe component cell performance, (b) for a-Si/nc-Si double junction solar cells, optimization of a-Si thin film and doped layer/buffer layer used for a-Si top cells, and device quality nc-Si bottom cells , and (c) for heterojunction solar cell, development of intrinsic a-Si for superior silicon wafer surface passivation, wafer surface texturing process, n-type a-Si thin films as window layers, and ITO layers. We attained 11% initial total area efficiency for a-Si/a-SiGe triple junction modules, and 12.8% initial total area efficiency for a-Si/nc-Si double junction modules, and 21.7% total area efficiency for heterojunction solar cells using n-type wafers.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115742249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The study of Shallow Trench Isolation gap-fill for 28nm node and beyond 28nm及以上节点的浅沟隔离补隙研究
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153405
Yu Bao, Xiaoqiang Zhou, Ningbo Sang, Tong Lei, Gang Shi, Hailan Yi, Bin Zhong, Jun Zhou, Fang Li, Yi Ding, Runling Li, Haifeng Zhou, J. Fang
{"title":"The study of Shallow Trench Isolation gap-fill for 28nm node and beyond","authors":"Yu Bao, Xiaoqiang Zhou, Ningbo Sang, Tong Lei, Gang Shi, Hailan Yi, Bin Zhong, Jun Zhou, Fang Li, Yi Ding, Runling Li, Haifeng Zhou, J. Fang","doi":"10.1109/CSTIC.2015.7153405","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153405","url":null,"abstract":"In this paper, a conception of Dep-Etch-Dep was proposed to extend the gap-fill capability of High Aspect Ratio Process (HARP) for Shallow Trench Isolation (STI) at 28nm node. Silicon oxide liner deposited by Atom Layer Deposition (ALD), which has no loading effect, can enlarge the process window. After the deposition of silicon oxide liner, an available multi-cycles SiCoNi dry etch process was applied to trim off the silicon oxide near the entrance, and got prefect V shape recess structure. Then, the STI was filled up with silicon oxide by HARP, and the seam was repaired during steam anneal. The TEM images showed good gap-fill performance using ALD-SiCoNi-HARP (ASH) approach.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123775214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The electromigration failure mechanism for TSV process TSV工艺的电迁移失效机理
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153453
L. Yong, A. Zhao, Canny Chen
{"title":"The electromigration failure mechanism for TSV process","authors":"L. Yong, A. Zhao, Canny Chen","doi":"10.1109/CSTIC.2015.7153453","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153453","url":null,"abstract":"TSV (Through Silicon Via) is the key component in fabricating 3D ICs and device packaging which has the advantages of lower power consumption, higher integration density and shorter interconnection length. TSV is a composite structure fabricated by process filling electroplated copper into etched silicon via, it consists of Cu/Ta/TaN/SiO2/Si multiple interfaces with roughness formed in the via etching process. In the TSV structure, more difference in coefficient of thermal expansion between copper and silicon leads to high thermal stress and related reliability issues, but fewer TSV EM works have been reported. Thus, TSV test structure with M1 of aluminum and backside redistribution layer of copper was designed and tested to evaluate EM reliability performance. Generally, the void nucleation and growth induce resistance change, and then impact expected metal interconnection performance. In our study, an unfamiliar EM failure mechanism of TSV was observed. No typical void was found, but barrier damage and Cu diffusion were observed in test. From failure analysis result, it is considered that EM failure mechanism of TSV consists of several major stages, including (1) barrier damage, (2) Cu diffusion and (3) CuAl alloy form. With the CuAl alloy formed, resistance of metal interconnection increases, so it induces EM failure.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125938123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The new methodology of contact process window vericification 接触过程窗口验证的新方法
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153354
Yi-Lung Fang, Siao-Ling Li, Hsiang-Chou Liao, T. Luoh, Ling-Wu Yang, Tahone Yang, Kuang-Chao Chen
{"title":"The new methodology of contact process window vericification","authors":"Yi-Lung Fang, Siao-Ling Li, Hsiang-Chou Liao, T. Luoh, Ling-Wu Yang, Tahone Yang, Kuang-Chao Chen","doi":"10.1109/CSTIC.2015.7153354","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153354","url":null,"abstract":"Generally CD (critical dimension) measurement is an important role for verify the FEM (Focus Exposure Matrix) process window. However, the generally CD measurement is rough due to only measure few site in wafer. The results cannot get the high accuracy information for verification the FEM process window and waste a lot of FEM process time. In this paper, we have demonstrate a new methodology that can get rapidly and precisely verify FEM process window by advanced CD measurement go through high resolution images and contour extraction.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122320741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High contrast mark used for in-situ UV nano-imprint lithography allignment 高对比度标记用于原位UV纳米压印平准
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153371
Li Ding, Jin Qin, Liang Wang
{"title":"High contrast mark used for in-situ UV nano-imprint lithography allignment","authors":"Li Ding, Jin Qin, Liang Wang","doi":"10.1109/CSTIC.2015.7153371","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153371","url":null,"abstract":"This paper focuses on designing a high contrast alignment mark used for imprint lithography in-liquid alignment. Since the imprint resist filled in the imprint pattern will deteriorate the intensity and contrast of the Moiré fringes, it's hard to perform alignment based on the Moiré image. Through coating optically dens materials inside the imprint mask and changing the material, thickness, etch depth and grating pitch size, higher contrast can be obtained. Simulations based on Rigorous coupled-wave analysis (RCWA) are performed to calculate the reflection efficiency and contrast of obtained Moiré fringes. Experiments demonstrated that the simulation result is correct and feasible.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128401084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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