{"title":"From the present to the future: Scaling of planar VLSI-CMOS devices towards 3D-FinFETs and beyond 10nm CMOS technologies; manufacturing challenges and future technology concepts","authors":"J. Hoentschel, A. Wei","doi":"10.1109/CSTIC.2015.7153333","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153333","url":null,"abstract":"Jan Hoentschel works for GLOBALFOUNDRIES as a Device Manager and is responsible for 28nm low power technologies. He manages an international device engineering team, which is handling several low power CMOS technologies starting from 40nm down to 28nm. Before he was working with Advanced Micro Devices and served several PD-SOI-CMOS device integrations from 130nm down to 32nm technologies for high performance microprocessors. In addition he was working within the product interaction and implementation group at AMD in Austin, TX. Jan Hoentschel is author and co-author of numerous technical papers and patents in the semiconductor field. He holds an MS and PhD in electrical engineering from the Technical University in Dresden as well as an MBA in General Management from the University of Applied Science Bielefeld. His research interests include HKMG, strain engineering, 3D FinFET device and technology concepts, lIIiV semiconductors and low power technologies on CMOS devices.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132019670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Yaegashi, K. Oyama, A. Hara, Sakurako Natori, Shohei Yamauchi, Masatoshi Yamato, Noriaki Okabe, K. Koike
{"title":"Enabling capability of multi-patterning towards 10nm and beyond","authors":"H. Yaegashi, K. Oyama, A. Hara, Sakurako Natori, Shohei Yamauchi, Masatoshi Yamato, Noriaki Okabe, K. Koike","doi":"10.1109/CSTIC.2015.7153363","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153363","url":null,"abstract":"Scaling in the manufacture of semiconductor devices has come to be supported by advances in photolithography technology. Looking to the future, we can expect even more advances in photolithography, but at present, multi-patterning using 193nm immersion lithography is finding widespread use as an alternative technology that can contribute greatly to even higher levels of integration in semiconductor devices in combination with 1D layout. However, given increasingly complicated processes and sharp jumps in cost impact with this approach, the ideal solution would be one based on the optical reduction projection method as in the past. We anticipate the appearance of EUV technology as a next-generation lithography technology that will achieve a complementary convergence with etching and film-growing techniques developed with multi-patterning technology.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"480 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132067460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Use soft-decision error-correction codes in Phase-Change Memory","authors":"Binbin Li, Bolun Zhang, Yifan Zhang, Dongmei Xue","doi":"10.1109/CSTIC.2015.7153460","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153460","url":null,"abstract":"Researches indicate that the resistance of phase-change material will become larger over the time. Use time-aware based soft-decision error correction code, which needs LLR to decode, can correct the errors in multilevel PCM effectively. Accurate LLR needs to read the resistance accurately, which will lead to a longer transmission latency. In this paper, we proposed a non-uniform correction strategy, which can reduce the read levels maintaining bit-error-rate performance. We use LDPC in correction of 4-level per cell PCM, and get the result via computer simulation.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130912610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Novel approach to CMP slurry filtration through new generation nano-fiber technology","authors":"H. Yang, Yi Wei Lu, Henry Wang, Bob Shie","doi":"10.1109/CSTIC.2015.7153419","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153419","url":null,"abstract":"Reduced device feature size and new device manufacturing processes require more efficient management and control of the chemical mechanical planarization (CMP) process. One of the key parameters to lower defectivity is to control contaminants through the use of a CMP filter operation [1]. This paper discusses CMP slurry filtration methodologies and mechanisms along with the relationship between particle retention and particle size. The “shearing effects” of slurries are also studied with a consideration of contamination control and filter lifetime comparing nano-fiber technology and conventional technology. This information is an essential consideration to optimize CMP slurry filtration operations.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131038720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Zhang Hongzhi, Zhang Kai-liang, Wang Fang, Han Yemei, Zhao Jinshi, Wang Baolin, Jian Xiaochuan, Sun Kuo
{"title":"Effect of VOx interlayer in Cu /HfOx/TiN cell and its resistive switching mechanism","authors":"Zhang Hongzhi, Zhang Kai-liang, Wang Fang, Han Yemei, Zhao Jinshi, Wang Baolin, Jian Xiaochuan, Sun Kuo","doi":"10.1109/CSTIC.2015.7153474","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153474","url":null,"abstract":"In order to improve the performance of HfOx-based resistive random access memory (RRAM), a VOx buffer layer was introduced in the Cu/HfOx interface of Cu/HfOx/TiN RRAM cell in this paper. Their resistive switching characteristics (such as I-V characteristics, endurance and retention) and the switching mechanism were investigated. Results show that the VOx buffer layer acts as a barrier which avoids excessive Cu ion reaching to HfOx layer as result to improve the device performances. The current conduction mechanism of low resistive state (LRS) is Ohmic conduction while the high resistive state (HRS) is Schottky emission. Based on the negative temperature coefficient of LRS resistance and conduction mechanism, we believe that the resistive switching between HRS and LRS is attributed to the Cu-CF's formation and rupture.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131212876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yi Ding, Yefang Zhu, Junhua Yan, Conggang Wang, Wenbin Fan, A. Pang
{"title":"Application of measurement method on Cu-CMP process","authors":"Yi Ding, Yefang Zhu, Junhua Yan, Conggang Wang, Wenbin Fan, A. Pang","doi":"10.1109/CSTIC.2015.7153423","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153423","url":null,"abstract":"Chemical Mechanical Polishing (CMP) is considered the only processing technique that can achieve high level of local and global planarity of wafer surface and therefore widely used on IC manufacture industry [1]. However, It becomes more difficult but important to monitor CMP process performance well. In this paper, Metapulse (provided by Rudolph) and Aleris8350 (provided by Kla-Tencor) were used to monitor Cu-CMP process. The theory and characteristic of these two measurement tools were studied by using two typical monitor structures (OCD pad and Bond pad) to monitor Cu-CMP process. Performance evaluation is based on mean, range, and uniformity. Our results show that Aleris8350 is suitable for dielectric measurement to reflect topography performance of the whole wafer and Metapulse has advantage in thickness measurement for both OCD pad and Bond pad.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128179341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Study of grain size and polishing performance of aluminum film as metal gate electrode","authors":"Xiaoniu Fu, Xiaona Wang, Jianhua Xu, Wufeng Deng, Ziying Zhang, X. Jing, Beichao Zhang","doi":"10.1109/CSTIC.2015.7153416","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153416","url":null,"abstract":"Aluminum (Al) film has been implemented in semiconductor manufacturing such as gap fill in the metal gate trench. Al-induced crystallization and layer exchange processes showed great impact on grain size, and Al grain size was varied by deposition rate and temperature. We investigated grain size of Al deposited on different substrates of p-Si, PEOX and thermal oxide by DC magnetron sputtering. Grain size and film roughness were characterized by SEM and AFM. The film polishing result was correlative with grain size, smoothness and continuous Al film showed better CMP performance, while larger grain size was easier to be pulled out by CMP.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116851018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
X. Tian, Qi Wang, H. Hou, Guangyu Chen, Guanchao Zhao, Rong Yang, Liwei Li, Y. Meng, T. Guo
{"title":"Pyramid size control and its effects on the performance of silicon heterojunction solar cells","authors":"X. Tian, Qi Wang, H. Hou, Guangyu Chen, Guanchao Zhao, Rong Yang, Liwei Li, Y. Meng, T. Guo","doi":"10.1109/CSTIC.2015.7153488","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153488","url":null,"abstract":"This paper explores the formation process of surface pyramid morphologies and etching characteristics during the texturing process of silicon heterojunction (SHJ) solar cells. Our research discovered that pyramid size followed a linear correlation with etch amount at the transition point of planes {100} to {111} as the etch rate reached the transition point. Several techniques were developed to control pyramid size by monitoring and adjusting the etching amount at the transition point. Using this approach, the average pyramid size was successfully controlled from 0.5 μm to 12 μm. We concluded that for pyramids smaller than 1 μm or greater than 12 μm, the light reflectance, minority carrier lifetime (MCLT), and performance of SHJ solar cells were adversely affected. In conclusion, a desirable range of pyramid sizes was empirically determined by our investigation.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"IM-34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126634656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Jin, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H. Wakabayashi, K. Tsutsui, K. Natori, H. Iwai
{"title":"An investigation of CeO2 based ReRAM with p+ and n+-Si bottom electrodes","authors":"J. Jin, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H. Wakabayashi, K. Tsutsui, K. Natori, H. Iwai","doi":"10.1109/CSTIC.2015.7153330","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153330","url":null,"abstract":"In this paper we use the p<sup>+</sup>-Si and n<sup>+</sup>-Si as bottom electrode for CeO<sub>2</sub> based ReRAM. The work function difference between p<sup>+</sup>-Si and n<sup>+</sup>-Si substrate gives out an about 0.6 V shift of the set and reset voltage. The mechanism of this shift was investigated and the set and reset of voltage with pulse width dependence was also concerned depends on p<sup>+</sup>-Si substrate.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"22 48","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113962887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The study of 28nm node poly double patterning integrated process","authors":"Zhonghua Li, Runling Li, Tianpeng Guan, Biqiu Liu, Xiaoming Mao, Xiangguo Meng, Quanbo Li, Fang Li, Zhengkai Yang, Yu Zhang, A. Pang","doi":"10.1109/CSTIC.2015.7153427","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153427","url":null,"abstract":"As the development of semiconductor devices, especially for 28 nm technology node and beyond, the shorten effect in line ends of poly gate will be challenging as the size grow smaller, resulting in the overlap of line ends of pattern in mask where Optical Proximity Correction (OPC) is already pushed to the limit. Therefore, the technology of poly line end cut (LEC) process is introduced to cut the long poly pattern for the desired short length, by introducing double patterning lithography. In this paper, we used 193nm immersion lithography for double patterning. A thorough integration scheme was explored and discussed, including film sketches and etching profile to achieve desired CD through double pattering.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114683131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}