{"title":"Challenges and characterization of 14nm N-type bulk FinFET","authors":"Yong Li, J. Ju, M. Liao","doi":"10.1109/CSTIC.2015.7153426","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153426","url":null,"abstract":"FinFET device has better electrostatic performance than planar device and makes devices further scaling possible. N-type bulk FinFET process challenges such as implantation induced Fin damages, Source/Darin (S/D) epitaxy and Fin profile control were discussed. Pre-Fin anti-punch trough (APT) implantation and low beam current n-type light-doped-drain (NLDD) implantation combined with optimized post-implant annealing are both benefit to eliminate or reduce the implantation induced Fin damages. Within S/D Si epitaxy process, contact resistance, resistor resistance and transistor external resistance were much reduced. With the optimized process, n-type bulk FinFET device performance was much improved. Gate oxide performance and electron mobility were compared with previous generations; swing slope and drain induced barrier lowering were also got from the IdVg curves. Some reliability evaluations such as GOI, TDDB and HCI were performed and passed the specifications. For n-type bulk FinFET further improvement directions were proposed at last.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132455881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Gu, Lin Zhang, Jin Wang, Mingchong Ren, Yan He, Juan Zhang, Zhan Xu, Guangyu Chen, Ling Dai, Guanchao Zhao, Qi Wang, Rong Yang, Liwei Li, Y. Meng, T. Guo
{"title":"Development of ito/layered a-P Si:H film stack for silicon heterojunction solar cells","authors":"S. Gu, Lin Zhang, Jin Wang, Mingchong Ren, Yan He, Juan Zhang, Zhan Xu, Guangyu Chen, Ling Dai, Guanchao Zhao, Qi Wang, Rong Yang, Liwei Li, Y. Meng, T. Guo","doi":"10.1109/CSTIC.2015.7153496","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153496","url":null,"abstract":"This work focuses on the development of integrated front side film stack containing a-p Si:H film as the emitter and ITO film as the carrier collection layer in n-type silicon heterojunction (SHJ) solar cells. Doping concentration and thickness of a-p Si:H films, and O2/Ar flow ratio of DC sputtered ITO films were varied to obtain optimal single layer properties. A combined ITO/double a-p Si:H stack was then developed and optimized to improve fill factor (FF) of SHJ solar cells. As a result, FF higher than 78% with conversion efficiency of 21.6% have been achieved in this work.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129344894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Method for analog-mixed signal design verification and model calibration","authors":"Chao Liang, Zhou Fang, C.-Z Chen","doi":"10.1109/CSTIC.2015.7153486","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153486","url":null,"abstract":"Traditional mixed-signal design verification is carried out separately by analog team who run transistor level simulation through different corners, and by digital team who run block simulation on RTL while using analog mixed-signal (AMS) behavior model to represent analog function. That method could not meet the verification requirements for advanced IP integrated SoC designs anymore. An integrated mixed-signal verification environment with Universal Verification Methodology (UVM) mixed-signal based testbench is introduced for subsystem verification, which supports different abstraction of analog design. In current work, traditional Verilog-AMS model was used first, followed by mixed mode AMS simulation in the same testbench in which analog IP was replaced with transistor level netlist to verify the possible missing points caused by inaccurate AMS model. The simulation based on AMS model discovered 27% issues, while mixed mode AMS simulation found 73%, which can hardly be found at RTL synthesis or downstream flow thus lead to fatal silicon chip. Additionally, analog assertions are used to check the analog design function, to validate that the AMS model is correct through using the same testbench as means of model calibration, in order to deliver high quality AMS model to SoC design team for chip level simulation.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126108924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H.-R. Ren, Chen-guang Gai, Jun Huang, Yu Zhang, A. Pang, Liyan Zhang, Lei Sun
{"title":"Optimization of 28nm M1 trench etch profile and ILD loss uniformity","authors":"H.-R. Ren, Chen-guang Gai, Jun Huang, Yu Zhang, A. Pang, Liyan Zhang, Lei Sun","doi":"10.1109/CSTIC.2015.7153378","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153378","url":null,"abstract":"Cu process and low-k material are wildly used to reduce Rc delay effect from 45nm technology node and beyond, dry etch to low-k material is one of big challenges in BEOL (Back-End-of-Line) process. For M1 trench etch, the main parameters, such as M1 trench CD, trench depth, trench profile, trench ILD loss uniformity and the connection between M1 & CT, will impact the result of M1 WAT (Rs and Capability) and Reliability. In this article the optimized trench profile and ILD loss uniformity for 28nm M1 etch was obtained by balancing various dry etch process parameters.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121815641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Characterization and improvement of immersion process defectivity in memory device manufacturing","authors":"Weiming He, Huayong Hu, Qiang Wu","doi":"10.1109/CSTIC.2015.7153369","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153369","url":null,"abstract":"As integrated circuit (IC) industry steps into immersion lithography's era, defectivity in photolithography becomes more complex which requires more efforts in the analysis and solution finding when compared to traditional dry lithographic process. In this paper, we focus on one type of immersion defects from memory or flash memory devices with typical mask layouts. Since the use of self-aligned double patterning (SADP) or other double patterning techniques, the original single pattern layer has to be split into 2 mask layers: logic area vs cell area. One characteristic of such split process is that the total mask transmission rate (TR) is above 70%, with both big open areas and a pattern area with a transmission rate close to 50%. This means that its defects characteristics can be a little different from logic devices. We have found that memory device is easier to suffer photoresist (PR) residue defects with center ring-like map. We have analyzed its underlying mechanisms and found optimized approaches to improve it by tuning parameters in development and rinse recipe. The results of our study will be presented and discussed.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130510801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Eberstein, K. Reinhardt, S. Korner, F. Kiefer, R. Peibst
{"title":"Glass phase alignment in front side pastes for P- and N-type solar cells","authors":"M. Eberstein, K. Reinhardt, S. Korner, F. Kiefer, R. Peibst","doi":"10.1109/CSTIC.2015.7153489","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153489","url":null,"abstract":"Using an in-situ contact resistance measurement silver pastes containing glass and aluminum additions for p- and n-type cells were investigated during rapid thermal process (RTP) firing. The glass viscosity, i.e. the formation of a liquid phase having a viscosity between 104 Pa·s and 105 Pa·s, is the crucial point for opening of the antireflection coating, regardless of the kind of wafer or aluminum addition. The maximum efficiency is obtained in an optimum between the competing effects silver precipitation and emitter corrosion and can be precisely time-resolved observed by an in-situ contact resistance measurement. The peak firing temperature determines the intensity of the interface reaction whereas the temperature related glass viscosity is crucial important for the reaction duration and acts as kinetic switch. In comparison to common pastes for p-type cells, in pastes with alumina additions for n-type cells the glass phase rearranges and depletes at the interface due to thermodynamic reasons. The rearrangement of the glass phase attenuates the reduction of silver in the interface layer and controls the solar cell contacting.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129637913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jian Xiaochuan, Zhang Kai-liang, Wang Fang, Han Yemei, Zhao Jinshi, Wang Baolin, Sun Kuo, Zhang Hongzhi
{"title":"Schottky-barrier modulated HfO2-resistive switching memory with ultra-low power","authors":"Jian Xiaochuan, Zhang Kai-liang, Wang Fang, Han Yemei, Zhao Jinshi, Wang Baolin, Sun Kuo, Zhang Hongzhi","doi":"10.1109/CSTIC.2015.7153473","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153473","url":null,"abstract":"To reduce the Reset current, the HfO2-based RRAM device with Ni top electrode (TE) and TiN bottom electrode (BE) is fabricated. Compared to the devices with Al and Ti top electrodes, the Ni/HfO2/TiN device cell with the high-work-function Ni TE exhibits the ultra-low Reset current (sub-100nA), bipolar resistive switching, consistent switching with a large window and good data retention. In addition, multilevel storage characteristics are demonstrated by setting different compliance currents during set processes. The ultra-low power characteristic is related to the Schottky barrier at the interface of high-work-function Ni TE and n-type HfO2. The mechanisms of resistive switching and current conduction are also analyzed based on the Schottky-barrier modulation.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128927019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Fan, Hungling Chen, Yin Long, Qiliang Ni, Kai Wang, Zhibin He, Zhengkai Yang, Yanyun Wang, Liang Ni
{"title":"The detection and investigation of SRAM data retention soft failures by voltage contrast inspection","authors":"R. Fan, Hungling Chen, Yin Long, Qiliang Ni, Kai Wang, Zhibin He, Zhengkai Yang, Yanyun Wang, Liang Ni","doi":"10.1109/CSTIC.2015.7153455","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153455","url":null,"abstract":"The research was aimed at the inline detection of the electron leakage leading to end-of-the-line soft failures. The electron beam inspection was applied to detect the voltage contrast signal by the PMOS leakage, and the leakage would lead to SRAM data retention failures in CP test during 40nm technology development. A series of experiments, including retargeting the CD of NP lithography process and re-tape-out the mask with new optical proximity correct (OPC), were set up according to the inline detectable VC inspection method, and an optimal process integration condition without failures was achieved.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122866083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Compressive sensing method for production chip test","authors":"Bolun Zhang, Yifan Zhang, Binbin Li","doi":"10.1109/CSTIC.2015.7153462","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153462","url":null,"abstract":"IC testing is an essential part of semiconductor manufacturing, the silicon chips are deserved to be tested and characterized carefully to get the variation information, however, the traditional testing methods suffer from time consuming, time costing and large area overhead. Compressive Sensing (CS) illustrates that a signal can be perfectly reconstructed from fewer samples than the Nyquist-Shannon sampling theorem requires. CS takes advantage of the signal's sparseness in some domains, allowing the entire signal to be determined from relatively few measurements. The Linear Dynamical System (LDS) framework is regarded as an important class of parametric models for time-series data. This paper designed an algorithm for the bulk production chip testing based on CS theory. The data to be tested is the numerical variations of chips one by one from the same lot, the purpose of our project is to recover all the data from limited few samples as accurate as possible, and the main idea is to estimate the LDS parameter from compressive measurements.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115840366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Yang, B. Li, F. Baumann, E. Huang, D. Edelstein, R. Rosenberg
{"title":"Enhanced electromigration resistance through grain size modulation in copper interconnects","authors":"C. Yang, B. Li, F. Baumann, E. Huang, D. Edelstein, R. Rosenberg","doi":"10.1109/CSTIC.2015.7153408","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153408","url":null,"abstract":"Grain size modulation in Cu interconnects was achieved at an elevated anneal temperature of 250 °C. As compared to the conventional annealing at 100 °C, the elevated process enabled further Cu grain growth, which then resulted in an increased grain size and improved electromigration resistance in the Cu interconnects. In order to prevent stress migration reliability degradation from the elevated annealing process, a TaN metal passivation layer was deposited on the Cu interconnect surface prior to the thermal annealing process, which suppressed void formation within the Cu features during the anneal process and reduced inelastic deformation within the interconnects after cooling down to room temperature.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131757109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}