{"title":"基于高k介电介质的MIM电容器的I-V不对称机理","authors":"W. Lau, D. Q. Yu, X. Wang, H. Wong, Y. Xu","doi":"10.1109/CSTIC.2015.7153403","DOIUrl":null,"url":null,"abstract":"MIM capacitors based on high-k dielectric are used in analog CMOS. They tend to show up an asymmetric I-V characteristics even though they may have an apparently symmetric structure; the same situation occurs for high-k dielectric deposited by CVD or ALD. In this paper, we will propose a physical mechanism for the asymmetric I-V characteristics observed and we will also provide experimental data to support our claim.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Mechanism of I–V asymmetry of MIM capacitors based on high-k dielectric\",\"authors\":\"W. Lau, D. Q. Yu, X. Wang, H. Wong, Y. Xu\",\"doi\":\"10.1109/CSTIC.2015.7153403\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"MIM capacitors based on high-k dielectric are used in analog CMOS. They tend to show up an asymmetric I-V characteristics even though they may have an apparently symmetric structure; the same situation occurs for high-k dielectric deposited by CVD or ALD. In this paper, we will propose a physical mechanism for the asymmetric I-V characteristics observed and we will also provide experimental data to support our claim.\",\"PeriodicalId\":130108,\"journal\":{\"name\":\"2015 China Semiconductor Technology International Conference\",\"volume\":\"42 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-03-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 China Semiconductor Technology International Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CSTIC.2015.7153403\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 China Semiconductor Technology International Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSTIC.2015.7153403","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Mechanism of I–V asymmetry of MIM capacitors based on high-k dielectric
MIM capacitors based on high-k dielectric are used in analog CMOS. They tend to show up an asymmetric I-V characteristics even though they may have an apparently symmetric structure; the same situation occurs for high-k dielectric deposited by CVD or ALD. In this paper, we will propose a physical mechanism for the asymmetric I-V characteristics observed and we will also provide experimental data to support our claim.
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