40nm offset spacer process optimization to improve device stability and mismatch

Abstract

Continuously shrinking of device CD imposes lots of demanding requirements on wafer manufacturing. In FEOL of wafer processing, device performance will be seriously impacted by the structure including AA/POLY/SPACER. Offset Spacer post Gate POLY increases LDD extension and improves short channel effect, which is a very important factor for good final device performance. This paper focuses on risk assessment for current HLMC 40nm offset spacer process. By changing offset spacer film and optimizing LDD/PKT implant are shown to improve SRAM device mismatch and Vccmin yield performance.