Hard mask profile and loading issue study in SADP process

Abstract

Double Patterning (DP) technique is developed and applied to 45nm technology node and beyond by improving litho equipment and process windows. In addition in the 14/16nm node, the planar device is replaced by 3D FINFET architecture for device performance improvement; the SADP (self-align double patterning) technique is developed for FIN formation with focus on the smaller CD and LER (line edge roughness) evolution. The challenges during process development are FIN profile loading, core film profile tuning and others. In this paper, the authors introduce FIN formation and the main challenges during process development.