Wafer edge overlay control for 28 nm and beyond technology node

Abstract

Advanced semiconductor industry requires chips with higher integration density and smaller critical dimensions, which means the overlay has to be shrunk in proportion. According to the International Technology Roadmap for Semiconductors (ITRS), the overlay requirement for 28 nm is 5.4 nm in 3-sigma. Generally speaking, this overlay requirement can be met with the current state-of-the-art exposure tools. Recently, researchers specifically look at the edge die overlay within a typical 140 mm to 147 mm range in wafer radius. The result is much worse than that of full map overlay. In this paper, multiple root causes of the bad edge overlay are discussed in detail. Among these contributors, un-optimized overlay sampling plan, high order alignment, chuck edge cleanliness, alignment strategy optimization and inappropriate baseliner sub-recipe generation method play major roles. In order to minimize the impact from these overlay contribution factors, corresponding solutions have been explored. Our conclusion is that the edge overlay can be minimized to some extent, while it's very challenging to bring the wafer edge overlay performance to the level of full map overlay.