发布求助
文献互助 智能选刊 最新文献

2015 China Semiconductor Technology International Conference最新文献

筛选
英文 中文
Capillary design contribution to the bonding process quality of NiPd-PPF leadframes with Cu & PdCu wires 毛细管设计对NiPd-PPF引线与Cu和PdCu导线粘合工艺质量的贡献
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153440
Langut Ilan, Zuri Limor, Gur Giyora
{"title":"Capillary design contribution to the bonding process quality of NiPd-PPF leadframes with Cu & PdCu wires","authors":"Langut Ilan, Zuri Limor, Gur Giyora","doi":"10.1109/CSTIC.2015.7153440","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153440","url":null,"abstract":"Package footprint reduction, environmental protection law compliance and manufacturing cost reduction constrains are moving the semiconductor industry toward the mass adoption of Quad Flat Non-leaded packages (QFN), Pre Plated Frames (PPF), and Cu based bonding wires. On the one hand, these chip packaging technologies enable compliance with these objectives, yet on the other hand they present new challenges to assembly houses and IC package manufacturers. This paper will discuss the influence of the capillary design, its material improvements and bonding process factors on the main challenges of bonding Cu and PdCu wires on NiPd-PPF leadframes, including QFNs. These challenges include low wedge bond strength, wedge bond deterioration over time, small wedge bond process window.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133092572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
32/28nm BEOL Cu gap-fill challenges for metal film 32/28nm BEOL铜隙填充金属薄膜的挑战
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153409
X. Jing, J. Tan, Jiquan Liu
{"title":"32/28nm BEOL Cu gap-fill challenges for metal film","authors":"X. Jing, J. Tan, Jiquan Liu","doi":"10.1109/CSTIC.2015.7153409","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153409","url":null,"abstract":"With the logic device size shrinking to 32/28nm and beyond, ultra- low k has been introduced to Cu interconnect, which makes Cu gap-fill very challenging. This paper has summarized metal hard mask, Ta(N) barrier, Cu seed and electroplating (ECP) challenges for 28nm BEOL Cu gap-fill. Metal hard mask thickness and stress greatly impact gap fill performance and need to be optimized. Thinner barrier helps meet gap-fill and Via Rc requirements, but it may compromise its reliability robustness. In order to have good Cu gap-fill at both trench and via, Cu seed needs to be optimized at top overhang and sidewall step coverage, or it requires a fair balance between the two tuning knobs. ECP chemical selection, additive concentration, and entry also show their critical roles in the gap-fill performance.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115924638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
The optimization of overlay control for beyond sub-40nm lithography processes 超亚40nm光刻工艺的覆盖层控制优化
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153346
Zhifeng Gan, Zhibiao Mao, Wuping Wang, Hui Zhi, Zhengkai Yang, Biqiu Liu, Yu Zhang
{"title":"The optimization of overlay control for beyond sub-40nm lithography processes","authors":"Zhifeng Gan, Zhibiao Mao, Wuping Wang, Hui Zhi, Zhengkai Yang, Biqiu Liu, Yu Zhang","doi":"10.1109/CSTIC.2015.7153346","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153346","url":null,"abstract":"The overlay performance in lithography process depends on both the machine control abilities and overlay residue control in processes. One of important optimization directions of lithography processes in advanced node is to decrease overlay residue in the lithography processes and the overlay margin must meet the stability requirement. In this paper, the investigation on the effect of alignment accuracy, reticle elasticity, and high order nonlinear components on the overlay accuracy are presented. Furthermore, the optimization of overlay performance based on the above factors is implemented to realize the high accuracy of overlay and ensure the process stabilities, paving the way for sub-40nm and beyond production requirement.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124154947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reciprocating surface grinding of semiconductor wafers: A kinematic model for grinding marks & pattern 半导体晶圆的往复表面磨削:磨削痕迹与图案的运动学模型
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153418
Qi Zhang, Zhichao Li
{"title":"Reciprocating surface grinding of semiconductor wafers: A kinematic model for grinding marks & pattern","authors":"Qi Zhang, Zhichao Li","doi":"10.1109/CSTIC.2015.7153418","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153418","url":null,"abstract":"Reciprocating surface grinding is one of state-of-the-art machining processes to flatten semiconductor wafers to obtain a better surface roughness and grinding marks uniformity. In this paper, a kinematic model is developed to study the grinding marks pattern resulted from the reciprocating surface grinding. The model is then utilized to simulate the grinding marks and compared with rotary surface grinding. Experiments are also conducted to verify the simulation results.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123697426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Metal hard-mask based AIO etch challenges and solutions 基于金属硬掩膜的AIO蚀刻挑战和解决方案
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153386
Jun-qing Zhou, Minda Hu, Qi-yang He, H. Zhang
{"title":"Metal hard-mask based AIO etch challenges and solutions","authors":"Jun-qing Zhou, Minda Hu, Qi-yang He, H. Zhang","doi":"10.1109/CSTIC.2015.7153386","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153386","url":null,"abstract":"Trench-first-metal-hard-mask (TFMHM) approach has been widely utilized for copper interconnect formation since 45nm CMOS technology node. In TFMHM process integration development, four major challenges have to be solved. The first is the gap-fill due to the small top trench CD and the introduction of metal hard mask; the second is to meet the electrical targets through lower capacitance, lower metal sheet resistance and lower via contact resistance; the third is to meet yield requirement that ensure no short, bridge and open in all the design rule allowed patterns, and eliminate all killer defects; the last is the reliability related issues including metal and via related TDDB, upstream EM and downstream EM. Coupled with the optimization of wet clean process and proper choice of metal hard mask, a smooth and tapered trench profile could be delivered and the gap-fill performance could be greatly improved. The optimization of barrier/seed process coupled with the desired trench profile, via bottom CD and via chamfer profile, the on-target electrical performance could be achieved. The via bottom CD and chamfer profile are also critical to interconnects and etch process parameter optimization is important for defect elimination. With partial SAV process optimization, via related TDDB issue is solved and trench related TDDB is also not a problem for the above gap-fill friendly trench profile. For EM, we found the downstream EM lifetime is improved by gap filling friendly process and proper copper line CD.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122039565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Sub resolution assist feature study in 28nm node poly lithographic process 亚分辨率辅助28nm节点聚光刻工艺特征研究
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153347
Xiaoming Mao, Zhengkai Yang, Xiaobo Guo, Zhifeng Gan, Biqiu Liu, Zhibiao Mao
{"title":"Sub resolution assist feature study in 28nm node poly lithographic process","authors":"Xiaoming Mao, Zhengkai Yang, Xiaobo Guo, Zhifeng Gan, Biqiu Liu, Zhibiao Mao","doi":"10.1109/CSTIC.2015.7153347","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153347","url":null,"abstract":"The semiconductor industry is being driven by “Moore's law” towards smaller and smaller feature sizes and pitches. The 28nm technology node is facing many challenges especially at the POLY layer lithography process, which is the most critical and tight pitch design. The double patterning technology (DPT) is proved to be an effective technology to enhance resolution; however, DPT hasn't been implemented on the 28nm tech node yet due to the concern of cost and process complexity. Therefore, others resolution enhancement technology (RET), such as Sub Resolution Assist Feature (SRAF) plays more critical role than before. In this paper, we studied how the SRAF setting affects the Depth of Focus (DOF) from view of both result of simulation and Si wafer verification. The DOF trend of multiple pitches from Si wafer verification is well matched with the trend simulation result. Furthermore, we found an interesting phenomenon that side-lobe occurring in some particular pitch pattern, the further study and experiment showed that the side-lobe could be suppressed by implementing SRAF.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129686266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Photolithography solutions for fabrication of Fin and Poly-gate in 14nm FinFET devices 在14nm FinFET器件中制造Fin和polygate的光刻解决方案
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153353
Xiaobo Guo, Xianguo Dong, Shuxin Yao, Zhifeng Gan, Wuping Wang, Zhengkai Yang, Ermin Chong, Quanbo Li, Zhibiao Mao, L. Zhang, Runling Li, Yu Zhang
{"title":"Photolithography solutions for fabrication of Fin and Poly-gate in 14nm FinFET devices","authors":"Xiaobo Guo, Xianguo Dong, Shuxin Yao, Zhifeng Gan, Wuping Wang, Zhengkai Yang, Ermin Chong, Quanbo Li, Zhibiao Mao, L. Zhang, Runling Li, Yu Zhang","doi":"10.1109/CSTIC.2015.7153353","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153353","url":null,"abstract":"Due to good electrical characteristics and controllability, 3D-FinFET is proved to be a promising substitution of planar poly-gate devices for 20nm technology node and beyond. One of the greatest challenges is to fabricate the Fin and Poly-gate to meet device requirement. This paper describes the photolithography process as one of key solutions to form Fin and Poly-gate structure in 14nm FinFET devices. To fabricate the Fin structure, SADP (Self Aligned Double Patterning) process is introduced to obtain 25nm half pitch pattern; furthermore, the overlay performance, which is impacted by SADP process, is studied on both design of alignment/overlay mark and light source of overlay measurement. Lithography performance of LELE (Lihto-Etch-Litho-Etch) double-patterning is described in poly line formation. LEC (Line End Cutting) process with various groups of materials is discussed to improve poly line-end performance. Finally, a desired FinFET structure is successfully fabricated.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129726735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Fabrication of 3D carbon structures based on C-MEMS technique (invited speaker) 基于C-MEMS技术的三维碳结构制备(特邀演讲嘉宾)
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153349
Shulan Jiang, T. Shi, Hu Long, S. Xi, Hu Hao, Siyi Cheng, Zirong Tang
{"title":"Fabrication of 3D carbon structures based on C-MEMS technique (invited speaker)","authors":"Shulan Jiang, T. Shi, Hu Long, S. Xi, Hu Hao, Siyi Cheng, Zirong Tang","doi":"10.1109/CSTIC.2015.7153349","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153349","url":null,"abstract":"Facile and low-cost strategies are devised for large-scale manufacturing of three-dimensional (3D) large surface area and high-aspect-ratio carbon structures using UV photolithography process along with pyrolysis process. Moreover, combined with self-assembly process, oxygen plasma etching process, film sputtering process, or electrochemically deposition process, various 3D large surface area carbon structures are obtained, including suspended glassy-like carbon microelectrodes, nanowrinkles integrated carbon microstructures, micro/nano dual-scale carbon array, etc. These large surface area carbon structures show great potentials in the fields of chemical and biological sensors, surface-enhanced Raman scattering, and energy storage devices such as micro-supercapacitors, micro-batteries and fuel cells. This paper provides an overview of our research on large-scale fabrication of 3D large surface area carbon structures.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130207453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Comprehensive investigation and design of Tunnel FET-based SRAM 基于隧道场效应效应的SRAM综合研究与设计
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153332
Hao Zhu, Qianqian Huang, Lingyi Guo, Libo Yang, Ye Le, Ru Huang
{"title":"Comprehensive investigation and design of Tunnel FET-based SRAM","authors":"Hao Zhu, Qianqian Huang, Lingyi Guo, Libo Yang, Ye Le, Ru Huang","doi":"10.1109/CSTIC.2015.7153332","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153332","url":null,"abstract":"In this work, the impacts of electrical characteristics of Tunnel FET (TFET) on the SRAM design are systemically investigated for the first time from the perspective of memory array. A novel 10T TFET SRAM design is also proposed to overcome the challenges and improve the circuit stability. By using a calibrated compact model, the simulated static power of 10T TFET SRAM can be much lower than traditional 6T MOSFET SRAM, especially at the low supply voltage of 0.5V. In addition, the cell's stability is also largely improved with the largest noise margin compared with reported 7T TFET SRAM design and traditional 6T MOSFET SRAM.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130817954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High H2 ash process applications at advanced logic process 高氢灰工艺在高级逻辑工艺中的应用
2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI: 10.1109/CSTIC.2015.7153385
Xiao-Ying Meng, Qiu-hua Han, Hai-yang Zhang
{"title":"High H2 ash process applications at advanced logic process","authors":"Xiao-Ying Meng, Qiu-hua Han, Hai-yang Zhang","doi":"10.1109/CSTIC.2015.7153385","DOIUrl":"https://doi.org/10.1109/CSTIC.2015.7153385","url":null,"abstract":"Both shallow junction and HKMG have been integrated into the advanced logic process. This leads to the introduction of forming gas (4% H2 in N2/H2 mixture) to replace the traditional O2-based ashing process for the sake of material loss and metal oxidization in Lightly Doped Drain ash. In this work, we focused on the high volume H2 ashing not only from the point of view of physical performance but also the yield enhancement. Compared with conventional forming gas ash process, high H2 ash process delivers superior photo resist removal capability, much less Si loss and higher throughput at high-dose implant strip. Besides, Si-C bond after p-MOS Si recess etch could inhibit SiGe epitaxy, thus resulting in defect. We proved that high H2 ash process could effectively remove the Si-C bond at EPI surface and greatly reduce the SiGe EPI defect count. In Static Random Access Memory vehicle, high H2 process delivers >10% Vmin yield enhancement. In brief, high H2 ashing process can benefit throughput, photo resist removal capability and yield enhancement for HKMG process.","PeriodicalId":130108,"journal":{"name":"2015 China Semiconductor Technology International Conference","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129189319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信