Photolithography solutions for fabrication of Fin and Poly-gate in 14nm FinFET devices

2015 China Semiconductor Technology International Conference Pub Date : 2015-03-15 DOI:10.1109/CSTIC.2015.7153353

Xiaobo Guo, Xianguo Dong, Shuxin Yao, Zhifeng Gan, Wuping Wang, Zhengkai Yang, Ermin Chong, Quanbo Li, Zhibiao Mao, L. Zhang, Runling Li, Yu Zhang

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引用次数: 1

Abstract

Due to good electrical characteristics and controllability, 3D-FinFET is proved to be a promising substitution of planar poly-gate devices for 20nm technology node and beyond. One of the greatest challenges is to fabricate the Fin and Poly-gate to meet device requirement. This paper describes the photolithography process as one of key solutions to form Fin and Poly-gate structure in 14nm FinFET devices. To fabricate the Fin structure, SADP (Self Aligned Double Patterning) process is introduced to obtain 25nm half pitch pattern; furthermore, the overlay performance, which is impacted by SADP process, is studied on both design of alignment/overlay mark and light source of overlay measurement. Lithography performance of LELE (Lihto-Etch-Litho-Etch) double-patterning is described in poly line formation. LEC (Line End Cutting) process with various groups of materials is discussed to improve poly line-end performance. Finally, a desired FinFET structure is successfully fabricated.

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在14nm FinFET器件中制造Fin和polygate的光刻解决方案

由于其良好的电特性和可控性，3D-FinFET被证明是20nm及以上技术节点平面多栅极器件的有前途的替代品。最大的挑战之一是制造Fin和Poly-gate以满足器件要求。本文介绍了光刻工艺作为在14nm FinFET器件中形成Fin和Poly-gate结构的关键解决方案之一。为了制造翅片结构，引入了SADP (Self Aligned Double Patterning)工艺，获得了25nm的半间距图案;在此基础上，从对中/覆盖标记设计和覆盖测量光源两个方面研究了SADP过程对覆盖性能的影响。描述了LELE(光刻-光刻-蚀刻)双图案在多线形成中的光刻性能。讨论了不同材料组的线端切割工艺，以提高多线端性能。最后，成功地制作出理想的FinFET结构。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2015 China Semiconductor Technology International Conference

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