Comprehensive investigation and design of Tunnel FET-based SRAM

Abstract

In this work, the impacts of electrical characteristics of Tunnel FET (TFET) on the SRAM design are systemically investigated for the first time from the perspective of memory array. A novel 10T TFET SRAM design is also proposed to overcome the challenges and improve the circuit stability. By using a calibrated compact model, the simulated static power of 10T TFET SRAM can be much lower than traditional 6T MOSFET SRAM, especially at the low supply voltage of 0.5V. In addition, the cell's stability is also largely improved with the largest noise margin compared with reported 7T TFET SRAM design and traditional 6T MOSFET SRAM.