32/28nm BEOL Cu gap-fill challenges for metal film

Abstract

With the logic device size shrinking to 32/28nm and beyond, ultra- low k has been introduced to Cu interconnect, which makes Cu gap-fill very challenging. This paper has summarized metal hard mask, Ta(N) barrier, Cu seed and electroplating (ECP) challenges for 28nm BEOL Cu gap-fill. Metal hard mask thickness and stress greatly impact gap fill performance and need to be optimized. Thinner barrier helps meet gap-fill and Via Rc requirements, but it may compromise its reliability robustness. In order to have good Cu gap-fill at both trench and via, Cu seed needs to be optimized at top overhang and sidewall step coverage, or it requires a fair balance between the two tuning knobs. ECP chemical selection, additive concentration, and entry also show their critical roles in the gap-fill performance.