IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.最新文献_第3页

Next generation electronics packaging utilizing flip chip technology 下一代电子封装利用倒装芯片技术

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. Pub Date : 2003-07-16 DOI: 10.1109/IEMT.2003.1225938

G. Pascariu, P. Cronin, D. Crowley

{"title":"Next generation electronics packaging utilizing flip chip technology","authors":"G. Pascariu, P. Cronin, D. Crowley","doi":"10.1109/IEMT.2003.1225938","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225938","url":null,"abstract":"This paper discusses the critical requirements for high volume flip chip die bonding. Product functionality for devices such as handheld telephones, laptop computers, and other personal electronic items has driven a trend towards compactness of design and improved packaging processes. The paper presents an overview of products and technologies utilizing flip chip packaging techniques today and in the future. It includes a discussion of the technical and cost drivers of flip chip packaging. Flip chip technology offers design and processing advantages. Design advantages include smaller device footprint, improved electrical performance, better thermal dissipation properties and lower cost due to better use of silicon real estate. Processing advantages include shorter assembly cycle times, fewer operations, and higher yields. A range of packages is available for flip chip packaging including FC-CSP, FC-BGA, HFC-BGA, and others. A comparison of these packages is presented including a comparison of I/O count and package size. The paper describes the advantages and applications for each of these package types. The methodology of flip chip die bonding is rooted in die bonding with some interesting modifications. Key components of the flip chip process are substrate handling along with die flipping and flux dipping. These process steps are presented with a detailed description from the initial point of picking the die through fluxing and to the actual placement of the die including material handling. Critical aspects of the flip chip die bonding process such as work holder planarity and flux control are discussed as the key to high yield, high volume production. Critical aspects of underfill dispensing such as process control and high throughputs are presented as the key to cost effective production.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125443581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 47

Backend processing for wafer level chip scale packaging 晶圆级芯片规模封装的后端加工

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. Pub Date : 2003-07-16 DOI: 10.1109/IEMT.2003.1225897

J. Hunt

引用次数: 1

Reduce your cycle time by utilizing automation for wafer test data collection 通过使用自动化晶圆测试数据收集来减少周期时间

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. Pub Date : 2003-07-16 DOI: 10.1109/IEMT.2003.1225900

N. Tandon, A. Sanchez, S. Arora, F. Yousuf, J. Miller, R. Elder

{"title":"Reduce your cycle time by utilizing automation for wafer test data collection","authors":"N. Tandon, A. Sanchez, S. Arora, F. Yousuf, J. Miller, R. Elder","doi":"10.1109/IEMT.2003.1225900","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225900","url":null,"abstract":"Many strategies are generally applied in the semiconductor industry to reduce cycle times. This technical paper describes an integrated automation environment that has been implemented on the various tester platforms at Kilby Center (KFAB) of Texas Instruments (TI). In addition to reducing wafer test cycle time, the tester automation eliminates human errors, which is an added benefit over vendor \"job tools\". The referenced automation environment integrates seamlessly with the manufacturing execution system (MES), and facilitates data collection in both file format and in an electrical test database. The automation flow typically includes the tasks of tester initialization, system processes' validation, tester hardware mini-diagnostics, probe card verification, test program load and execution, data upload to MES and test database, validation of collected test data, execution of lot disposition, and lot movement/hold in MES. However, there are differences across multiple tester platforms provided by different equipment vendors. In addition to detailing the automation components of tester platforms, the paper highlights the cycle time impacts.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121693954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Advanced design, technology & manufacturing for high volume and low cost production 先进的设计，技术和制造，大批量，低成本的生产

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. Pub Date : 2003-07-16 DOI: 10.1109/IEMT.2003.1225910

L. Lecheminoux, N. Gosselin

{"title":"Advanced design, technology & manufacturing for high volume and low cost production","authors":"L. Lecheminoux, N. Gosselin","doi":"10.1109/IEMT.2003.1225910","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225910","url":null,"abstract":"Over the last years, the Low Temperature Co-fired Ceramic (LTCC) technology has proven its extreme efficiency for compact and reliable radio-frequency (RF) modules for wireless communication. LTCC technology is widely present in switches, power amplifiers and Bluetooth modules for handsets. No doubt that this technology will also be adopted for the WLAN (wireless local area network) modules in a very short term. However LTCC solutions often suffers from the reputation to be difficult to design, few flexible and expensive specially versus the very well known solutions based on printed circuit boards (PCB). DT Microcircuits and Thales Microelectronics launched together an important study to simplify the design and reduce the cost of WLAN modules based on LTCC technology. This paper summarizes this 12 months study. RF designers studied the different architectures and integration levels applied to WLAN modules. Fundamental elementary blocks, like baluns, filters, power amplifiers (PA) and switches were identified and described as a function of possible architectures, specifications and pre-selected technologies. They were implemented in LTCC substrates individually and all together. Several more or less complex LTCC modules were designed, simulated, manufactured and tested. The study proved the ability to efficiently implement the different components of a WLAN front-end module (FEM) in LTCC, whatever the chosen technologies and architectures: embedded LTCC components (filters, switches), surface acoustic waves (SAW) filters, PIN diodes or GaAs switches and PA. It allows customers to save an important time in the design of their WLAN LTCC modules.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124601782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Pre-project facility and layout planning for setting up cost effective wafer bumping processes 项目前期设施和布局规划，以建立具有成本效益的晶圆冲压工艺

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. Pub Date : 2003-07-16 DOI: 10.1109/IEMT.2003.1225928

M. Wu, Y.G. Jin, S. Quek, S. Huang

{"title":"Pre-project facility and layout planning for setting up cost effective wafer bumping processes","authors":"M. Wu, Y.G. Jin, S. Quek, S. Huang","doi":"10.1109/IEMT.2003.1225928","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225928","url":null,"abstract":"With the emergence of flip chip technologies in semiconductor assembly, a great deal of attention has been given to infrastructures such as wafer bumping services, equipment manufacturers, material and substrate suppliers. Little has been said about facility planning and design for flip chip processes. When rapid shifts in technology take place, optimum planning of facility layout is of great importance for productive manufacturing processes in term of cycle time, yield, quality control, and sustainability. This paper explores a facility layout design using Simplified Systematic Layout Planning (SSLP) techniques prior to the wafer bumping setup. Other techniques such as experiential, cloning, strategic or Bottom-up are difficult, if not impossible, to be applied in a process with new technological requirements. In this study, a \"ball room\" design is compared with \"cellular\" design by analyzing four basic elements: space planning units (SPUs), affinities, space, and constraints at the Macro-Space Plan level. The cellular layout arrangement is more cost effective than the ballroom design, however at the expense of its flexibility for future changes and upgrading. In this case, a low value-added space ratio is used to compensate the inflexibility. Differentiated cleanroom modules are designed for the sub-processes of wafer bumping so that the areas of high-grade cleanroom (ISO Class 5) are minimized. The final layout plan is further evaluated by using positive-negative-interesting (PNI) and material flow analysis (MFA) tools. In addition, special attention is paid to the integration of new and existing processes.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"760 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133119771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An approach to reduce build up layers for flip chip-ball grid array (FC-BGA) substrates 一种减少倒装晶片球栅阵列(FC-BGA)基板累积层数的方法

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. Pub Date : 2003-07-16 DOI: 10.1109/IEMT.2003.1225889

T. Nishio, K. Kazushige, Y. Yamaji, N. Takahashi, K. Masanori, R. Malfatt

引用次数: 1

Technical and economic requirements of integrated SOC testing 集成SOC测试的技术和经济要求

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. Pub Date : 2003-07-16 DOI: 10.1109/IEMT.2003.1225903

D. W. Blair

{"title":"Technical and economic requirements of integrated SOC testing","authors":"D. W. Blair","doi":"10.1109/IEMT.2003.1225903","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225903","url":null,"abstract":"The consumer and business demand of integrating more functionality into a single device is causing the level of integration of today's system-on-a-chip (SOC) ICs to accelerate faster than ever before. IC design and manufacturing technologies have also converged to make this possible as never before. Some examples of this are Set-Top-Box/Cable Modems (STB/CMs), cell phones with PDA and video imaging and DVD R/W systems. These types of integrated SOCs can have digital, memory, mixed signal, and RF challenges, and a true SOC tester must combine all of these capabilities to address these challenges. However, meeting the technical challenges is not enough because these are high volume applications that demand low cost of test to make them economically feasible. This is also why the tester architecture must integrate all these different capabilities-single insertion testing is a must to meet the economic goals of devices in a consumer market. The particular technical and economic requirements of the SOC device need to be understood and then mapped into tester capability and the cost-of-test (COT) associated with high volume production. To understand what it takes to test this class of SOC, a STB/CM and a DVD R/W application will be used as examples. Typical block diagrams will be explored and solutions to some of the biggest technical challenges will be developed. High volume manufacturing will then be evaluated to reduce the COT to its minimum.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126065440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An innovative underfill process for high-speed SMT CSP BGA flip chip assembly 一种创新的高速SMT CSP BGA倒装芯片组装的下填工艺

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. Pub Date : 2003-07-16 DOI: 10.1109/IEMT.2003.1225872

Jian Zhang, D. Baldwin

{"title":"An innovative underfill process for high-speed SMT CSP BGA flip chip assembly","authors":"Jian Zhang, D. Baldwin","doi":"10.1109/IEMT.2003.1225872","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225872","url":null,"abstract":"Fluxing underfill materials are widely used in electronics manufacturing to improve reliability performance. The prevailing process of applying fluxing underfill is by dispensing the desired volume onto the printed circuit board with optimized patterns. The underfill cure is accomplished concurrently with solder joint formation in the reflow process. Even though the processing time of applying underfill material by this method is much shorter than that of the conventional capillary flow underfill process, the processing time of underfill dispensing is much longer than other process steps (e.g., printing, chip placement, reflow, etc). The current underfill dispensing process is a bottleneck in the high-speed electronic assembly manufacturing. Besides the long processing time, the underfill dispensing process requires complicated and expensive dispensing machines, which increase the manufacturing cost. In this research, an innovative dispenseless fluxing underfill process and the associated module have been developed to achieve high-speed SMT compatible underfill processing. The underfill application and chip placement are integrated into one process step that is accomplished by one placement machine. The prototyping of flip chip on board assemblies utilizing this innovative process shows dramatically reduced processing time. It also improves the reliability of electronic assembly systems. This invention enables remarkable cost savings from shortening processing time and eliminating the capital cost associated with underfill dispensing machines. The proposed process and module are fully compatible with the current SMT electronic manufacturing infrastructure. The dispenseless underfill process provides a high-speed and cost-effective solution for flip chip, CSP, and BGA electronic packaging assembly.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126181044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

In situ ball bond shear measurement using wire bonder bond head 用焊丝粘结机粘结头进行原位球粘结剪切测量

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. Pub Date : 2003-07-16 DOI: 10.1109/IEMT.2003.1225879

J. Medding, M. Mayer

引用次数: 10

WLCSP back-end considerations WLCSP后端注意事项

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. Pub Date : 2003-07-16 DOI: 10.1109/IEMT.2003.1225896

T. Tessier, W. S. Shin, Y. Yuen, B.T. Do, F. Kuan, J. Ling

引用次数: 0