An approach to reduce build up layers for flip chip-ball grid array (FC-BGA) substrates

Abstract

Flip Chip-Ball Grid Array (FC-BGA) packages with build-up type organic carriers have been focused towards implementing high I/O counts and electrical performance requirements. Many products utilize 2 build up layers on 2 core layers which is a total of 6 layers with 2-2-2 structure. Three or four build up layers are utilized for higher performance requirements. It is clear that layer count reduction would improve the cost performance for the FC-BGA. This paper shows an approach, using advanced technologies, to reduce 1 build up layer from 2 build up layers product applications of the FC-BGA keeping same I/O counts, electrical performance and reliability. The power plane for simultaneous switching noise, the high speed signal integrity and the structural analysis to compare the warpage and the stress will be applied to confirm the cost performance of the approach.