IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.最新文献

{"title":"Wafer bumping technology for LDI application by electroless nickel plating","authors":"J. Kim, Y.-N. Kim, J. Lee, J. Park, H. Kim, J.-O. Kim","doi":"10.1109/IEMT.2003.1225920","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225920","url":null,"abstract":"Electroless nickel layer has been used to provide an under bump metallization on the aluminum bond pads, as part of low cost wafer bumping process, prior to solder deposition. Recently, it has also found increasing use in wafer bumping for LDI(LCD for Drive IC) type device. However, the application of electroless nickel to the LDI wafer bumping is limited by the fact that bath stability of nickel is closely related with passivation opening size. In the present work, the effects of nickel bath parameters of stabilizer concentration, temperature and pH on the formation of electroless nickel bump have been investigated and optimum process conditions for LDI bumping were suggested. The measurements of bump surface and height distribution have been performed for the bump quality estimation by optical microscope and thickness profiler.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115636145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Inter-dependence of processing and alloy composition on the reliability of Sn-based lead free solders in fine pitch FCOB interconnection","authors":"Zhiheng Huang, P. Conway, Changqing Liu, R. Thomson","doi":"10.1109/IEMT.2003.1225885","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225885","url":null,"abstract":"Market demands and legislation are driving the electronics manufacturing sector to move rapidly toward for a lead free future, with Pb containing electronics products are to be banned in Europe from 2006. The UK readiness for joining global actions to enable this 'green' packaging urgently requires the replacement of SnPb with suitable lead free alloys. Although the related scientific research has been undertaken for a decade, a number of technical complications still exist, which are further exaggerated due to the concurrent developments of the new technologies needed for the miniaturisation and multi-functionality of microelectronic products. As the packaging joint geometry shrinks towards a microscopic scale, the joint fabrication and reliability become extremely sensitive to the composition and resulting microstructure generated from an essentially hybrid joining process. The current level of understanding on such issues is still in its infancy and therefore requires further fundamental study. Thermodynamic modelling is employed in this work as a major computational tool to study the sensitivity of processing ranges (e.g. reflow temperature) and the resultant reliability of the micro-joints by changing the alloying elements and their content in Sn-based lead-free systems. The work is implemented using the MTDATA program developed by the National Physical Laboratory (NPL), UK. With a newly-developed database containing critically assessed thermodynamic data appropriate for lead free solder systems, MTDATA allows the prediction of the dependence of the liquid-solid transformation and phase formation, for example, as a function of chemical composition and temperature. The paper emphasises the formation and mass fraction of intermetallic precipitates of different phases in the bulk solder joints and the modelling is also validated through carefully designed experimental work and recent literature. The results are expected to assist the optimisation of processing parameters and cost-effective production using lead free solders.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"45 14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114258716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Wire bond short reduction by encapsulation","authors":"A. Hmiel, C. Rutiser","doi":"10.1109/IEMT.2003.1225878","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225878","url":null,"abstract":"It is common place in the semiconductor packaging industry to inspect wires and remove shorts by rework prior to molding, in order to maximize yield. This process creates technical and commercial challenges for ultra fine pitch devices, multiple layers of wires, and stacked die applications. An alternative, automated method of removing wire shorts is presented in this paper. Experimental results demonstrate that the controlled application of a filled polymer with tailored rheology and surface tension can separate electrically shorted wires. This paper shows the separation of wires in cross sections of encapsulated devices, electrical test results of 35 /spl mu/m bond pitch devices pre and post-encapsulation, and discusses the physics that make this process possible. The packaging process and the process impact on device yield are also described.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130644136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Manufacturing issues for 3D integrated active circuits into organic laminate substrates","authors":"E. Jung, D. Wojakowski, A. Neumann, A. Ostmann, R. Aschenbrenner, H. Reichl","doi":"10.1109/IEMT.2003.1225915","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225915","url":null,"abstract":"The three dimensional integration of active circuits, thinned or in standard thickness, into polymeric substrates challenges current substrate manufacturing processes in an unprecedented way. In order to overcome the risks associated with this 3D integration technology, the issues must be carefully studied and assessed. For the direct integration of ultrathin chips into dielectric build up layers of multi-layer printed circuit boards, such issues were identified and put to the test using advanced pcb manufacturing methods. Among the risks encountered in a manufacturing ambient Material selection (i)linear tolerance on a 18/spl times/12\" board (ii)placement of ultrathin dice (iii)lamination process (iv)laser/plasma via formation (v)electroless deposition of seed layer (vi)patterning of the contact structures (vii)testing voltages were observed to be the ones affecting the outcome and will be discussed.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134541400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation of solder ball attachment processes","authors":"D. Geiger, D. Shangguan, D. Rooney","doi":"10.1109/IEMT.2003.1225942","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225942","url":null,"abstract":"There is a great deal of interest in methods to attach solder balls to substrates for various applications. In this work, different ball attachment methods are evaluated. In particular, two methods are evaluated in detail, including the paste printing and reflow method, and the ball placement method. Different solder alloys are included in the study. Solder ball dimensional accuracy, shear strength, and voiding are also characterized.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133344163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Epoxy flux - an answer for reliable no-clean flip chip assembly","authors":"W. Yin, G. Beckwith, H. Hwang, L. Kresge, N. Lee","doi":"10.1109/IEMT.2003.1225936","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225936","url":null,"abstract":"A novel epoxy flux PK-001 is developed and tested for no-clean flip chip attachment processes with tin-lead eutectic solder bumps. Results indicate that soldering and flux residue curing can be accomplished with a single reflow process. PK-001 provides adequate solder wetting and excellent non-voiding behavior for flip chip applications. The latter is attributable to its low volatility at above solder melting temperature. The uniformity of joint coverage area enables a tight soldering quality control. This is particularly crucial for high I/O count flip chip applications. The thermoset flux residue nature allows good compatibility with underfills, particularly under high temperature and high humidity conditions. Low ionics content, low corrosivity, and high SIR performance provide the essential remaining properties required for no-clean applications.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115185286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"BMI resins as low-stress alternatives to epoxies for semiconductor package assembly","authors":"C. Perabo","doi":"10.1109/IEMT.2003.1225912","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225912","url":null,"abstract":"Recent industry analyses indicate that higher-reliability, non-hermetic packages continue to be the trend in semiconductor packaging. Higher reliability means higher levels of JEDEC level performances (JEDEC L1) at higher reflow temperatures (260/spl deg/C). Similar studies also indicate that companies are not willing to pay higher costs for the materials required to meet these harsher conditions, so improved-performance organic materials are still critical for these applications. Though it is becoming more obvious to manufacturers that adhesives exist to provide low-cost solutions to these issues, most package-level manufacturers only consider epoxy chemistries to be reliable enough to be used for their applications. High purity, low-stress X-bismaleimide (X-BMI) resins however, can offer significant advantages over rigid epoxies and have been used in production applications for over a decade. Though not widely understood, they are suitable for a range of die-attach, lid-sealing, underfilling and bonding applications for semiconductor package or heat-generating devices to provide stable thermal performance. These low-cost solutions are achieved while providing rapid, in-line processing. This paper will focus on the role of BMI resins as low-stress alternatives to rigid epoxies semiconductor package assembly.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129436983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Testing high-speed serial interface technology: is your test solution in synch?","authors":"Steve Lomaro","doi":"10.1109/IEMT.2003.1225940","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225940","url":null,"abstract":"High-speed serial interface technology provides orders of magnitude improvement in device-to-device data transfer rates. Some interfaces are based on the use of clock forwarding-also known as source synchronous timing. The test challenges associated with this new technology are significant. Bit cell widths are shrinking to well under 1 ns, operating differentially and all timed to a jittery clock source. This is not a simple incremental improvement in existing technology; rather it is a paradigm shift in device interfaces. This paper reviews the background, illustrates why this interface is a test challenge, and explores solutions.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129088949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A comparison of electrical performance between a wire bonded and a flip chip CSP package","authors":"S. Pan, R. Kapoor, A. Sun, C. K. Wang, H. Low","doi":"10.1109/IEMT.2003.1225888","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225888","url":null,"abstract":"In this paper, electrical simulations are performed to characterize a wire-bonded window CSP (wCSP/sup TM/) package and a flip chip CSP (fcCSP) package designed for the same die. Results indicate that fcCSP has a slightly wider bandwidth than window CSP. Although, window CSP has a larger parasitic resistance and inductance for the target nets, it has a lower crosstalk in terms of peak-peak voltage due to shorter parallel traces. An optimized flip chip design is proposed and the results show a vast improvement over the wire bonded CSP package. Parametric studies are also performed to investigate the effects of bond wires with different diameter and horizontal distance, and variations in signal traces. These results provide useful insights on design and process selection for high-performance semiconductor packages.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131057655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of leadframe design on aluminum wire bonding","authors":"Tan Joo Hong, C. Kwee","doi":"10.1109/IEMT.2003.1225880","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225880","url":null,"abstract":"Parameters such as Force, Power, Time, Clamping and Anvil block designs are important factors in obtaining a good aluminum wedge bond. Initially, the leadframe design has a fused lead connected to the die paddle. This connection of the lead to the die paddle causes ineffective clamping, resulting in lifted wedge bond after reliability stress. Moreover, the bonding is worsened by delamination at the leads, found after stress. In this study, investigations are done on the leadframe designs to determine the effectiveness of the clamping concept that lead to good bond integrity. Pull tests results showed that the wedge bonds bonded on Partial Cut leadframe (with narrow joint between the lead and die paddle) are slightly weaker as compared to those bonded on Full Cut leadframe (no joint between the lead and die paddle). Moreover, propagation of delamination is seen on the Partial Cut lead. This phenomenon is however, not observed on the Full Cut lead. Thus, further reliability stresses are performed on the Full Cut leadframe design to further check on the bond integrity. All units passed the reliability tests and the package is qualified as a Moisture Classification Level 3 package.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125517876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}