A comparison of electrical performance between a wire bonded and a flip chip CSP package

Abstract

In this paper, electrical simulations are performed to characterize a wire-bonded window CSP (wCSP/sup TM/) package and a flip chip CSP (fcCSP) package designed for the same die. Results indicate that fcCSP has a slightly wider bandwidth than window CSP. Although, window CSP has a larger parasitic resistance and inductance for the target nets, it has a lower crosstalk in terms of peak-peak voltage due to shorter parallel traces. An optimized flip chip design is proposed and the results show a vast improvement over the wire bonded CSP package. Parametric studies are also performed to investigate the effects of bond wires with different diameter and horizontal distance, and variations in signal traces. These results provide useful insights on design and process selection for high-performance semiconductor packages.