Testing high-speed serial interface technology: is your test solution in synch?

Abstract

High-speed serial interface technology provides orders of magnitude improvement in device-to-device data transfer rates. Some interfaces are based on the use of clock forwarding-also known as source synchronous timing. The test challenges associated with this new technology are significant. Bit cell widths are shrinking to well under 1 ns, operating differentially and all timed to a jittery clock source. This is not a simple incremental improvement in existing technology; rather it is a paradigm shift in device interfaces. This paper reviews the background, illustrates why this interface is a test challenge, and explores solutions.