IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.最新文献_第2页

Reducing the cost of package Test 降低封装测试成本

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. Pub Date : 2003-07-16 DOI: 10.1109/IEMT.2003.1225905

S. Shakeri

引用次数: 0

Living daily with "monster" probe cards 每天与“怪物”探针卡一起生活

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. Pub Date : 2003-07-16 DOI: 10.1109/IEMT.2003.1225941

Frank Pietzschmann

引用次数: 0

Flip chip on standard lead frame: laminate performance at a lower cost 标准引线框架上的倒装芯片:以较低的成本实现层压板性能

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. Pub Date : 2003-07-16 DOI: 10.1109/IEMT.2003.1225907

F. Juskey

{"title":"Flip chip on standard lead frame: laminate performance at a lower cost","authors":"F. Juskey","doi":"10.1109/IEMT.2003.1225907","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225907","url":null,"abstract":"Flip Chip (FC) technology has been used for the last 30 years for high density, thermally challenging, high-speed IC packaging requirements. Originally done on very expensive ceramic substrates for mainframe computers, the technology was given a great boost forward by the implementation of the lower cost laminate-based PBGA technology. While laminate technology provided a significant cost, weight, and lead-time reduction in packaging technology, that helped revolutionize the PC and laptop computer markets, this still left a significant portion of the IC using marketplace unable to afford the benefits of FC technology. This paper discusses the advent of FC technology in low cost lead frame based IC packages for wireless, automotive and consumer electronic applications. By selectively engineering the die layout and by applying new and improved redistribution, bumping, and assembly technologies it is possible to take non-pad limited die and redistribute its I/O to a 200, 300, or 400 micron pitch and use the existing conventional lead frame IC packages infrastructure. The abbreviated assembly process and the re-use of existing tooling allows for a significant reduction in overall tooling charges. These new IC packages while having the same outward appearance, have a significant improvement in moisture sensitivity level (MSL), electrical performance, and in many instances where the die can be exposed, improved thermal performance at a cost significantly below that of laminate based FC technology.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114812600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Characterization of in-process substrate warpage of underfilled flip chip assembly 欠填充倒装芯片组装过程中衬底翘曲的表征

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. Pub Date : 2003-07-16 DOI: 10.1109/IEMT.2003.1225916

Jian Zhang, Hai Ding, D. Baldwin, I. C. Ume

引用次数: 8

Towards a halogen-free package - green molding compound 迈向无卤包装——绿色成型复合材料

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. Pub Date : 2003-07-16 DOI: 10.1109/IEMT.2003.1225886

Jong Kee, J. Yip

{"title":"Towards a halogen-free package - green molding compound","authors":"Jong Kee, J. Yip","doi":"10.1109/IEMT.2003.1225886","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225886","url":null,"abstract":"Green packaging has been a subject of interest and development in semiconductor manufacturing in recent years. At present, encapsulation of semiconductor devices is based on conventional material, which contains halogen, and antimony (Sb). Unfortunately, such elements are a hazard to the environment and health. The alternative is to replace these elements with environmentally friendly flame retardant system which is halogen-and antimony-free, thereby giving rise to the name of green molding compound. In this paper, five green and one conventional molding compounds are discussed. The intention is to select a green compound which has good performance in terms of processibility and reliability. The conventional compound serves as a reference for the five green compounds. The evaluation began with material characterisation which gave a preliminary insight into the general compound behaviour. During material characterisation, several relevant thermo-mechanical properties were compared, such as coefficient of thermal expansion (CTE) and glass temperature (Tg). Moisture absorption, adhesion strength, flexural modulus and filler content will also be discussed. Thereafter, thermal-mechanical simulation was performed to study the stress distribution of the test package with the different compounds. The test package was also subjected to preconditioning at JEDEC level 1 at a 3/spl times/ 260/spl deg/C reflow temperature to ascertain its extent of delamination at various interfaces. As the test package is used in automotive application, an additional 100x temperature cycling at -55/spl deg/C/+150/spl deg/C was included in the preconditioning condition. This is the standard practice for automotive products. With the results from the various evaluation models, the best green molding compound was selected and confirmed through an additional temperature cycling (TC) test at -55/spl deg/C/+150/spl deg/C 1000x.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132757526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

2D or 3D? benefits of combining both in a single X-ray system 2D还是3D?将两者结合在一个x射线系统中的好处

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. Pub Date : 2003-07-16 DOI: 10.1109/IEMT.2003.1225933

U. E. Frank

引用次数: 0

Current challenges in traditional design verification and its application in flip-chip devices 传统设计验证面临的挑战及其在倒装器件中的应用

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. Pub Date : 2003-07-16 DOI: 10.1109/IEMT.2003.1225901

I. Goldberger, S. Kasapi

{"title":"Current challenges in traditional design verification and its application in flip-chip devices","authors":"I. Goldberger, S. Kasapi","doi":"10.1109/IEMT.2003.1225901","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225901","url":null,"abstract":"The acceleration of new developments in semiconductor design and manufacturing technology in keeping up with Moore's Law has introduced significant new challenges for device designers as well as manufacturing organizations. Short channel effects, multi-level interconnect cross talk problems, and new materials such as low K dielectric, copper, and silicon on insulator have made modeling and simulation of semiconductor devices and processes extremely difficult. Many times this results in failure to meet performance targets in first silicon introduction. The high cost of mask sets, together with the opportunity costs related to time-to-market, drives the need for shorter and fewer redesign cycles, making effective transistor level design debug a necessity. To make things even more difficult, the transition to flip chip packaging and multiple interconnect metal layers makes backside probing the only effective way to perform node level analysis. This paper describes these new challenges in detail, and the use of photon probing technology as an effective way to address them. The use of a time resolved photon emission microscope allows measuring performance at the critical node level. This is done by collecting the photons, emitted by carriers that are accelerated in the pinch off region during CMOS transistor switching. This enables optimization of device speed paths, and resolution of problems such as race conditions and contentions, encountered during design debug and failure analysis cycles.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116579030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Study of non-solder, low cost and high performance flip chip QFN package using ultra thin Pd PPF 采用超薄Pd PPF的无焊料、低成本、高性能倒装QFN封装研究

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. Pub Date : 2003-07-16 DOI: 10.1109/IEMT.2003.1225874

Se Chuel Park, Chul-Lae Cho, Sung-Kwan Paek

{"title":"Study of non-solder, low cost and high performance flip chip QFN package using ultra thin Pd PPF","authors":"Se Chuel Park, Chul-Lae Cho, Sung-Kwan Paek","doi":"10.1109/IEMT.2003.1225874","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225874","url":null,"abstract":"For the development of semiconductor package, size reduction and high performance are driving forces. As increasing hand held products and green round issue, all package companies are interesting in study of package using lead free solder. As the today's package trend, many kinds of flip chip packages are developed using lead free solder. In most of flip chip packages, lead free solder or Au has been employed mainly as wafer bump, and Sn or Ag plated leadframe based on copper as a substrate. Solder as an interconnection material has been adopted. This study describes the performance of low cost, non-solder and green round package using flip chip interconnection technology on a Pd pre-plated leadframe (Pd PPF). The conventional leadframe couldn't be heated over 270 because of copper peel off. Although Pd-PPF could be workable in higher temperature than other type Cu leadframes, Conventional Pd-PPF showed that the poor thermal resistance for flip chip bonding process at high temperature. Therefore, in this study, newly developed a high quality and ultra thin Pd-PPF (AuAg finished Pd PPF) could provide proper surface condition and soluble substances. This leadframe could be applied to flip chip interconnection in wide temperature range. In conception of low cost, the electroless Ni/Au bump was used for flip chip interconnection with AuAg finished Pd PPF. The shear force of direct-bonded package was 23.05 mgf//spl mu/m/sup 2/. We used thermal compression bonding method and bonding condition is as following: chip temperature 380 and leadframe 380. As leadframe temperature being increased, shear force of the package was very steeply increased. The interconnected layer between the bump and the pre-plated leadframe was composed of Ni/AuAg/Pd/Ni.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131032838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Bumping wafers via ultrasonically enhanced stencil printing 通过超声增强的模板印刷来碰撞晶圆片

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. Pub Date : 2003-07-16 DOI: 10.1109/IEMT.2003.1225923

F. Andres, C. Lee, G. Pham-Van-diep

{"title":"Bumping wafers via ultrasonically enhanced stencil printing","authors":"F. Andres, C. Lee, G. Pham-Van-diep","doi":"10.1109/IEMT.2003.1225923","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225923","url":null,"abstract":"Traditional solder paste stencil printing is widely used and a well understood process in surface mount board assembly. But when applied to solder bumping wafers, stencil printing faces several challenges such as meeting bump height, co-planarity and voiding requirements. There are physical limitations within stencil printing that limits solder paste deposits at extremely tight pitches. Recent work has demonstrated that stencil printing can produce greater and more reliable material transfers at tighter pitches when high frequency vibrations are applied to the stencil at the time of stencil/substrate separation. This paper examines the feasibility of using conventional stencil printing coupled with an innovative ultrasonically enhanced procedure to offer a cost effective, flexible technique for solder wafer bumping. The effects of applying a high frequency vibration to a variety of stencil designs will be examined for wafer bumping applications. Paste development, reflow and process optimization will be discussed. Work will focus on bumping wafers with 250 /spl mu/m pitch and 100 /spl mu/m bump height. Bump height distribution, co-planarity performance and die yield per wafer are examined to determine the viability of the technique.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132965101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Overcoming test challenges presented by embedded flash memory 克服嵌入式快闪记忆体所带来的测试挑战

IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. Pub Date : 2003-07-16 DOI: 10.1109/IEMT.2003.1225899

J. Agin, H. Boyce, T. Trexler

引用次数: 4