IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.最新文献

{"title":"Lead-free package interconnections for ceramic grid arrays","authors":"Mario J. Interrante, Jeffrey Thomas Coffin, M. Cole, I. D. Sousa, M. Farooq, L. Goldmann, C. Goldsmith, J. Jozwiak, T. Lopez, G. Martin, V. Troung, D. Welsh","doi":"10.1109/IEMT.2003.1225883","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225883","url":null,"abstract":"As the electronics industry moves to eliminate lead from its components and solder assembly processes, new challenges arise in developing reliable interconnect processes. For the surface mount attachment of multilayer ceramic packages, this challenge becomes increasingly difficult in second-level assembly because of the large coefficient of thermal expansion (CTE) mismatch between the ceramic chip carrier and epoxy glass printed circuit board (PCB). The Ceramic Column Grid Array (CCGA) technology has shown itself capable of withstanding this mismatch, for tin-lead assembly, with high reliability while extending the 32 mm practical body size of CBGA ceramic packages to 52.5 mm. Lead-free interconnect structures have been developed for second-level assembly of ceramic grid array packages. For smaller packages where a ball structure provides sufficient thermal fatigue life, a standard lead-free Tin-Silver-Copper (SnAgCu or SAC) ball may be used. SAC CBGA interconnections have been shown to provide better reliability than their predecessor tin-lead dual alloy CBGA interconnections, when tested under accelerated thermal cycling conditions. The results from recent evaluations of CBGA packages will be discussed. For larger packages that require enhanced thermal fatigue life of the interconnection, a new lead-free column structure is being introduced. The Copper Column Grid Array (CuCGA) replaces the high-lead solder column with a copper column, which achieves electrical properties and mechanical fatigue characteristics that are comparable to the existing tin-lead CCGA packages. Modeling and measurement of the electrical performance for various column lengths and diameters aided in the selection of a column geometry to meet or exceed electrical performance of existing tin-lead columns. The influence of the metallurgical and physical properties of the column on the fatigue life of the system was also considered. The thermal fatigue failure mode differs from that typically seen in tin-lead CCGA packages.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121323820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Highly reliable photoimageable dielectric resins for wafer level CSP redistribution","authors":"C. Esposito, E. Yamayoshi, M. Yonehara, K. Arao, K. Yoshida, Shenghua Li, M. Kondoh","doi":"10.1109/IEMT.2003.1225894","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225894","url":null,"abstract":"The use of photoimageable dielectric resins for rewiring of WL-CSP's and passivation is increasing dramatically. Initial material selection for WL-CSP dielectrics was made from passivation materials. High processing temperatures, high shrinkage, difficult processing, poor adhesion, and poor electrical or thermal-cycle reliability are problems often experienced with these materials. A highly reliable epoxy based dielectric resin was designed specifically for use on wafer substrates. Excellent physical properties and extremely low shrinkage were obtained with low temperature cure schedules. Excellent electrical and thermal-mechanical properties gave superb reliability and fine resolution was obtained using alkaline development. This paper will focus on advancements made with regards to photolithography, thermal-mechanical properties, adhesion, and reliability.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115329274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Board level reliability evaluation of RF PA module vias","authors":"R. Darveaux, Jicheng Yang, A. Syed, B. Buella, P. Villareal, W. Kang","doi":"10.1109/IEMT.2003.1225918","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225918","url":null,"abstract":"The reliability of RF PA module substrate vias was evaluated using nine different laminate constructions. Variables in the substrate construction included layer count, trace thickness, via wall thickness, via diameter, via plugging, via capping, core material, and process flow at the supplier. A daisy chain module was designed to simulate a typical over molded RF PA module. The body size was 10/spl times/10 mm, with 2 die, 20 components, and 34 LGA I/O pads. Daisy chain nets were formed through 2 via chains, and 1 SMD component chain. Via reliability was measured by temperature cycling at -55/spl deg/C <=> 125/spl deg/C, 2 cph, after pre-conditioning at Jedec L3/240/spl deg/C and L3/260/spl deg/C. Both package level and board level testing was conducted. In the package level tests, it was found that nearly all of the constructions passed the typical qualification requirement of 1000 temperature cycles. However, one construction had failures starting at 600 cycles due to cracks in the knee region of the substrate vias. This construction used a less robust manufacturing flow at the substrate supplier. Three of the nine constructions were evaluated in the board level tests. All three legs passed the 1000 temperature cycle requirement, with the first via failure observed at 1372 cycles. No 2nd level solder joint failures were observed before the test was terminated at 3779 cycles. This robust board level temperature cycling performance is due to large NSMD pads (0.8 mm/spl times/0.8 mm), and small die (1.0 mm/spl times/1.0 mm). Failure analysis was conducted on all test legs to understand crack initiation sites and crack growth paths in the substrate vias.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115456967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Package stacking in SMT for 3D PCB assembly","authors":"D. Geiger, D. Shangguan, S. Tam, D. Rooney","doi":"10.1109/IEMT.2003.1225911","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225911","url":null,"abstract":"The need for continued miniaturization, functional densification and integration in handheld electronics products provides the strong incentive for printed circuit board (PCB) assembly in three-dimensions (3D). One way to accomplish 3D assembly is through the use of die stacking in chip scale packages (CSP), where the dice are stacked internally in the package. The other way to accomplish 3D assembly is through the use of package stacking. This is the process where two packages are placed on top of each other during the traditional surface mount placement process and then soldered together during the SMT (surface mount technology) reflow. In this paper, package stacking as part of the SMT process is described. The process, materials, and solder joint formation are characterized, and key issues highlighted.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131989583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Characterization of a spray acid tool for selectively etching under bump metallurgy films used in flip chip applications","authors":"L. Ramanathan, D. Mitchell","doi":"10.1109/IEMT.2003.1225919","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225919","url":null,"abstract":"A methodology for optimizing and characterizing processes for selectively etching Cu underbump metallurgy in the presence of Pb-Sn solder in spray acid tools is discussed. Wafers with the following UBM and bump structure were used in this study: sputtered TiW/sputtered Cu/electroplated Cu stud/electroplated Pb-Sn solder. The development of a manufacturable etch process is illustrated by discussing the method used to establish the process for selectively etching the sputtered Cu film using a commercial, two-component, ammoniacal Cu etch chemistry. The average etch rate on monitors with blanket sputtered Cu films, placed in all slots of the tool clamshell, was used to establish a non-uniformity factor (/spl eta/), which is defined as the ratio of the etch rate in the slot displaying the fastest etch rate to the etch rate in the slot displaying the slowest etch rate. Under ideal conditions the non-uniformity factor should be unity. Over the parameter space investigated it was found that the non-uniformity factor was minimized with the following conditions: temperature of 27/spl deg/C, RPM of 20, pump pressure of 52 psi, etchant flow rate of 6 liters/min, and a 25% solution of the two-component etch chemistry, with the two-components in a 1:3 proportion. Flip chip packages containing electroplated Cu stud and solder bump structures require selective etching of the underlying underbump metallurgy layers that serve as a diffusion barrier and as an electrical bus layer for the electroplating process. In this paper the characterization of a spray acid tool for selectively etching the sputtered Cu bus layer from multiple wafers simultaneously is discussed. The use of the non-uniformity parameter, /spl eta/, defined earlier, to establish the preliminary process is presented. /spl eta/ was also used to understand the parameters that controlled the uniformity of the spray pattern. In particular the effect of pump pressure, flow rate, and etchant composition on /spl eta/ was used to establish the levels of these variables for the Cu etch process. The preliminary Cu etch process was confirmed with a full lot containing 25 blanket Cu wafers. A maximum overetch of 39% was obtained for the full lot.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123466672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Advances in 300 mm wafer level packaging-new concepts of material deposition technologies","authors":"T. Oppert, J. Kloeser","doi":"10.1109/IEMT.2003.1225922","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225922","url":null,"abstract":"Survival in today's competitive electronics market continues to depend on advances on manufacturing technology. For example, the transition to 300 mm wafers has become for many semiconductor manufacturers inevitability in their highly cost-sensitive market. The whole Advanced Packaging Business is growing enormously and the push for wafer-level packaging is driven by the high potential to save cost by advanced bumping processes. Area Array Packages (Flip Chip, CSP and BGA) require the formation of bumps for the board assembly. Here cost effective bumping methods are needed which are not limited by the throughput, minimal pitch and yield. The industry is currently searching for new and lower cost bumping approaches to avoid high investment costs for the process equipment. Furthermore, in the field of advanced packaging there is a demand for high process flexibility. This includes that other materials like adhesives or epoxies must be deposited on the wafer or on boards. Due to the demand of the industry to transfer the production to 300 mm wafer these deposition processes must be suitable for this wafer size.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129124696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"3D stacked packages with bumpless interconnect technology","authors":"C.W.C. Lin, S. Chiang, T.K.A. Yang","doi":"10.1109/IEMT.2003.1225906","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225906","url":null,"abstract":"Novel 3D stacked packages fabricated with bumpless interconnect technology are presented. The single stacking unit can contain bare chips, packaged devices or passive components. An array of compliant terminals, or a series of copper pillars along the chip periphery are used as z-axis interconnects. To keep each single stacking unit thin, bumpless interconnect methods such as electro-chemical plating (ECP) or ball bonding are applied to connect the traces to the die pads directly. No wire bonding, lead-bond, solder bumps, substrate or vacuum sputtering films are involved. The traces route the pad to the z-axis interconnects (e.g., copper pillar, compliant terminal) which are orthogonal to the trace for 3D stacking assembly. Single stacking units are positioned in a vertical stack with their pillars and/or terminals aligned to one another. A single reflow operation simultaneously bonds all unit assemblies together to form the 3D stacked package. The compliant and deformable nature of solder paste and the routing traces provide flexible vertical interconnections that accommodate chips and packages with a wide range of thicknesses and sizes. The traces, pillars and/or compliant terminals serve as the interconnect matrix between the chips and packages, which may be functionally similar or different from one another, thereby increasing packaging density and functionality. Details of the design concepts, processing and the underlying bumpless interconnect technology are discussed along with key advantages and applications of these novel 3D stacked packages.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130139263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Stacked chip scale packages: manufacturing issues, reliability results, and cost analysis","authors":"J. Demmin, D. Baker, Wael Zohni","doi":"10.1109/IEMT.2003.1225908","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225908","url":null,"abstract":"System requirements for high density packaging have driven the development of chip scale package (CSP) technology. Continuing pressure for improved performance and reduced cost is dictating even greater improvements in functional density. A prime example of this can be found in the escalating requirements for DRAM and other memory modules. Functional integration within the silicon and bare chip stacking are two approaches to these challenges, but they present problems related to cost, time-to-market, testing, and business logistics. Stacking of tested CSPs - rather than bare chips-can address each of the issues because of increased design flexibility, the ability to extend the life of existing products, an established manufacturing infrastructure, and elimination of the technical and business challenges associated with procuring and testing bare die. With proper design, CSP stacking is a straightforward extension of standard packaging and surface mount processes. This paper reviews the manufacturing flow for one such stacked CSP technology, the /spl mu/Z/sup TM/-Ball Stack package. For any such high volume process, reliability is a critical issue, and reliability results for stacked CSP structures are presented. Most often, cost is the ultimate deciding factor in the selection of manufacturing technology, and a detailed cost analysis of package stacking versus die stacking is also presented. Much of the benefit can be found in the impact of the packaging technology on other parts of the supply chain, so the scope of the cost analysis extends beyond just the cost of the package. This approach can be used for analysis of any CSP stacking technology.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121158949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Extreme high speed microvia drilling of chip and wafer scale packaging products","authors":"T. Lizotte, O. Ohar","doi":"10.1109/IEMT.2003.1225932","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225932","url":null,"abstract":"The research and development of the optical system described was due in part to the virtual stalemate of current microvia drilling technology within the high density interconnect marketplace. The desire by industry to acquire faster processes for drilling microvias led to our research in the utilization of hybrid optical systems, where standard refractive and computer generated diffractive optics could be meshed to create a system that would out perform the current technology in the marketplace today. The outcome of this work is covered in the following paper and will at the outset briefly cover the architecture and the technology behind the laser optical beam delivery system and the unique components that make up the assembly. The laser beam characteristics at several points along the beam delivery will be discussed as well as the final image formed at the target plane, where the microvias are drilled and the importance of proper shape on target. Specific performance details will be shared with regards to total system performance. The final section will cover materials processing including the general process rate increases and microvia hole quality achieved.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126180681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A memory supplier's outlook on die products","authors":"D. Skinner","doi":"10.1109/IEMT.2003.1225898","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225898","url":null,"abstract":"Mobile PCs and servers, wireless handsets, personal appliances and other mobile applications are driving the need for high-performance, low-cost, small form factor memory solutions. For this reason, die products as well as integrated packaging technologies are increasingly more prevalent as memory solutions designed into these applications. System designs are increasingly implementing integrated packaging strategies, such as the multichip package (MCP) or stacked package and system in package (SiP) products. The growth in die product demand is reflected in semiconductor manufacturers development of new production and test processes to enable the production of die products with a higher yield. The applications integrating die products are diverse, each one with its own form factor and device characteristic requirements. The emergence of several new packaging and die product solutions offers designers options and the ability to pick the technology that best meets their design requirements. The wafer level chip scale package (WLCSP) is an example of an emerging packaging technology. WLCSP with a redistribution layer (RDL) applied provides many advantages over the standard thin small outline package (TSOP) and ball grid array (BGA) packages including electrical, thermal, and mechanical properties.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125210585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}