IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.最新文献

{"title":"The impact of moisture in mold compound preforms on the warpage of PBGA packages","authors":"T. Lin, B. Njoman, D. Crouthamel, K. H. Chua, S. Y. Teo, Y. Y. Ma","doi":"10.1109/IEMT.2003.1225913","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225913","url":null,"abstract":"The moisture in the mold compound preforms influenced the resultant mechanical properties as well as the warpage of IC packages after molding and post mold curing (PMC) process. The moisture will diffuse into the mold compound preforms (compound pallet) after thawing from cold room and exposing to the clean room condition before molding process. The moisture will swell the package and combine with thermal stress, and finally result in the warpage of molded package after molding process. The main objective of this paper is to address the impact of moisture in the compound preforms on the warpage of the PBGA packages and explain the resultant mechanical properties changes under the different moisture conditions, e.g., the variations of the flexural modulus, Tg, and CTE with respect to the moisture level. The actual compound preforms exposure to a clean room condition, were simulated by a series of experiments. The warpage of PBGA packages were measured in terms of moire test. The moisture control during the IC manufacturing process was highlighted in terms of the mechanical properties variation and warpage measurement due to the moisture effects on the mold compound performs.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132092311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The benefits of a flux-free atmosphere for wafer bump reflow","authors":"P. Lemieux, T. Tong, K. Brown","doi":"10.1109/IEMT.2003.1225924","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225924","url":null,"abstract":"There is constant pressure in semiconductor packaging to reduce costs while maintaining process yields. Wafer Level Packaging has increased in response to this pressure so that for the first time the packaging cost can remain constant despite the increasing number of die per wafer. The combination of shrinking pitch sizes and environmental regulations, causing materials changes, will make this even harder in the coming years. To keep costs down many wafer bump reflow processes use flux to reduce solder oxidation. However, the cost benefits of flux may not hold up when the total costs of the process are examined. We will examine using flux for wafer bump reflow including the impact on manufacturing and environmental considerations. The increased need for process cleanliness as it relates to flux and flux contamination will also be discussed. We will discuss alternatives to flux for oxide reduction. Specifically, Hydrogen atmosphere reflow will be examined including mechanism for oxide reduction and safety considerations. We will discuss the convergence of the needs for technology and cost reduction and form a conclusion on the best solutions to meet the needs of wafer bump reflow for leading technologists in the coming years.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133188890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"40Gb/s demonstration of IBM standard alumina BGA packages","authors":"W. Dyckman, E. Pillai, L. Shan, J. Trewhella, D. O'connor","doi":"10.1109/IEMT.2003.1225890","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225890","url":null,"abstract":"For the proliferation of 40Gb/s high speed links to become a reality, highly cost-effective as well as innovative interconnect technology approaches must be available in a standardized product. One critical facet of the 40Gb/s OC-768 is the challenge of packaging the front-end chips that run at the serial link data communication rate. This paper describes the packaging of 40Gb/s MUX using unique, innovative and robust transmission structures and an improved BGA using IBM's mature alumina MLC material set. Critical performance data showing transmission eye diagrams for both a GPPO surface mount connectorized module and a through BGA module are included. The design of a-newly patented coplanar waveguide (CPW) structure that is embedded in standard IBM alumina package materials is described as an example of one through BGA solution. The combination of the high performance RF structures and enhanced BGA has shown that IBM standard alumina can be readily used at 40Gb/s to produce a very cost effective solution that can be produced with standard tooling while incorporating lead free compatible BGA with standard bond and assembly processes. The product also features new advanced thermal solution that incorporates direct substrate attachment and utilizes thermal conduction through the package in addition to the module lid. This extends the thermal performance of the inherently high thermal density chip in the module to accommodate the 70/spl deg/C ambient thermal environment required by the OC-768 system specification.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"179 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133400287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Qualification and optimization of Sn based soft solders: A refinement for Bi based lead free soft solders for EFM volume production","authors":"B. Ong","doi":"10.1109/IEMT.2003.1225881","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225881","url":null,"abstract":"Continuous drive for environmental friendly manufacturing (EFM) has driven lead free soft solder to come on board at a larger scale world-wide since it was first debated publicly in 1999. Several renowned lead free soft solder suppliers have proposed Bi based soft solder as the most suitable candidate to replace the current widely used tin-lead (SnPb) solder. Experience with Bi out of material characterization lab has proven otherwise when used for die attach in power application devices. Composition of BiAgNi or equally synthesized alloys having Bi more than 45% have garnished poor wettability performance and presented brittle characteristic in term of solder wire handling. Oxidation is also seen prevalent in high temperature die mounting, and thus resulting in die bond failed to secure a good adhesion. As such, rule against stringent requirement of minimum 260/spl deg/C secondary pre-conditioning temperature should be reconsidered. Other low liquidus point lead free soft solders like Sn based SnSb & SnSbCuNi (241/spl deg/C to 247/spl deg/C) are put on test for the qualification process. This paper delineates the qualification processes & its response tests for the aforementioned soft solders between supplier and end-user, a 3 factors 2 levels DOE in optimizing the finalized lead free soft solder for die attach process and its reliability performance on thermal resistance shift. Results shown Sn based soft solders are sustainable and performed better than Bi based soft solders for volume EFM production.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129313379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Control of tin/lead solutions for electrodeposition of bumps","authors":"P. Bratin, E. Shalyt, M. Pavlov, J. Berkmans","doi":"10.1109/IEMT.2003.1225934","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225934","url":null,"abstract":"Typical bumping process includes formation of bumps through UBM copper electrodeposition, followed by deposition of tin/lead coating. Quality control of the tin or tin/lead electroplating solutions is critical to meet demands on the properties of the plated deposit, cost, and environmental issues. Even though lead is being phased-out as enemy of environment and many replacements are being tested, it is still widely used. As all electrochemical processes, tin/lead plating is a dynamic system; unless precisely controlled, concentration of consumable components and breakdown products soon gets outside of acceptable range resulting in manufacturing problems and eventually rejects. Copper Electrodeposition process for bumping is similar and somewhat less challenging than Damascene copper electrodeposition process used for the interconnects. The control of the Damascene copper process has been a focus of research by all major semiconductor companies in recent years. We have previously demonstrated an on-line controller for complete analysis of copper electroplating solutions. This paper will focus on automated on-line determination of tin/lead coatings, by reviewing analysis of up to 6 components in a commercial tin/lead electrodeposition bath. While the benchtop analysis of tin/lead solutions has been utilized for a number of years, many obstacles exist when transitioning such procedures into automated on-line system due to steps such as gravimetric or extraction procedures. While determination of metals and acid is reasonably common, measurement of proprietary organic additives remains a challenging task. Organic additives are the key ingredients in the plating solution that influence the properties and quality of the deposits. Cyclic Voltammetric Stripping (CVS) method is an established analytical technique that has long been demonstrated to be applicable to analysis of tin and tin/lead additives in various plating solutions (fluoroborate, sulfate, MSA, and PSA). Detailed description was published in an earlier paper. This paper will describe an on-line analysis of all components generally used in a tin/lead bumping process. The total automated analysis takes about 40-60 minutes with accuracy better than 10% and reproducibility better than 5%.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130916606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Implementation of Pb-free bumping in power packaging","authors":"R. Joshi, Miguel Rios, C. Tangpuz, E.V. Cruz","doi":"10.1109/IEMT.2003.1225882","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225882","url":null,"abstract":"MOSFETS are three terminal devices used in energy conversion switching applications. Rds-on is a key metric in assessing the efficiency of the switching solution. Chip and wire interconnect in MOSFET packages generally leads to a solution where the package parasitics significantly affect the overall product Rds-on. The industry has made rapid advances in the last few years to adopt flip chip interconnect. Due to the temperature hierarchy in processing (e.g. use of soft solder die attach for heat dissipation and provide a good electrical contact) the metallurgy of the flip chip required it to be compatible with high temperature processing. The Pb-free solution is required to be very cost effective and amenable to high volume manufacturing due to the nature of the use. Moreover, some recent form factors such the FLMP (Flip Chip in a Leaded Molded Package) and the MOSFET BGA allowed the die to be directly attached to the printed circuit board. The road to defining and implementing a Pb-free solution for bump interconnect for these applications is all the more difficult as the solution to be backward compatible with Pb-based paste as well as with Pb-free paste and yet retain its high temperature stability. Our paper gives details of this novel solution which by its very nature is very cost effective compared to other methods of achieving the same end results. Preliminary reliability results will be presented along with our work in simulating some environments through finite element analysis.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115724676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Towards next-generation design-for-manufacturability (DFM) frameworks for electronics product realization","authors":"M. Bajaj, R. Peak, M. Wilson, Injoong Kim, T. Thurman, M. C. Jothishankar, M. Benda, Pedro Ferreira, J. Stori","doi":"10.1109/IEMT.2003.1225930","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225930","url":null,"abstract":"This paper elucidates the process architecture of a pilot implementation of a DFM Framework (specifically the SFM DFM Framework or SDF), which consists of four key ingredients. The first ingredient is a Design Integrator that acquires product design information from an ECAD tool and in-house sources (each populating a subset of the design) and consolidates them into a STEP AP210 model. The second ingredient is a Rule-based Expert System (initiated at Boeing) that captures the manufacturability constraints as DFM rules and evaluates printed circuit assembly (PCA) designs against them. The third ingredient is a Design View Generator that extracts design information from the AP210 model (first ingredient) and library database and derives a Kappa design model for the expert system (second ingredient) to evaluate. The fourth ingredient is the Results Viewer that helps the user browse DFM analysis results and identify design improvement opportunities. This implementation of the SDF demonstrates the ability to extract PCA design information and build a higher fidelity standards-based design model. Additionally, it also shows the capability of Rule-based Expert Systems to emulate manufacturability checks on product (PCAs in this case) designs as well as increase analysis coverage and reduce human checking time via automation.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114073316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability ground rules change at <50 /spl mu/m pitch","authors":"I. Singh, L. Levine, J. Brunner","doi":"10.1109/IEMT.2003.1225875","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225875","url":null,"abstract":"Qualification of a new 40 /spl mu/m pitch wire bonding process requires significant process improvements and evaluations demonstrating process capability and reliability. Recent changes in the morphology of the ball bond, required to achieve high yield manufacturing with the largest diameter wire possible at this pitch, have changed the failure mode for high quality bonds. With newly developed high-strength bonding wire long-term aging is a critical task. Choice of failure criteria and test requirements are critical to success. These must assure long-term reliability and must also reflect reality. Ultra-fine pitch bonding on probed bond pads can significantly effect process yields and intermetallic formation. Device designs that separate probe and wire bond placement within a rectangular bond pad are preferred.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114440422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation of a lead-free flip chip assembly process","authors":"G. Kums, N. Duan, J. Scheer, M. van Kleef, J. Wijers, J. Bielen","doi":"10.1109/IEMT.2003.1225884","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225884","url":null,"abstract":"The integration of passive components into a single chip was developed to meet the increasing demands on cost and size reduction of the current RF power amplifier modules. Flip chip assembly on a laminate substrate using lead-free solder bumps was used for the module level assembly. In this paper, the detailed investigation of the assembly process is reported. This includes, among others, solder paste printing, flip chip placement and underfill application. The challenge of this flip chip assembly was the lead-free processing in both first level and second level interconnects and the required short throughput time from the pre-development to the mass production in the factory. First an orientation study was performed to find an optimum process window and two potential underfill candidates. Samples were made with the optimum process setting. To verify the process feasibility, thermal shock testing, moisture sensitivity assessment and high temperature storage testing were carried out. The reliability test results showed that one type of underfill performed very well, while another one could not meet the reliability requirements. The root failure cause with the troublesome underfill was found not to be caused by the assembly process but to be related to the underfill material and the via construction in the substrate.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123053680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Unique fiducial designs for CSP singulation process","authors":"P. Vijchulata","doi":"10.1109/IEMT.2003.1225870","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225870","url":null,"abstract":"This paper describes the invention of unique designs of fiducial marks on the ball pad side of substrates for different CSP (Chip Scale Package) integrated circuit package types and sizes. These unique designs on the substrates are related to the saw singulation process in the assembly of this type of packages. The distinct, unique fiducial designs enable the PRS (Pattern Recognition System) of the saw singulation equipment to differentiate between different molded CSP substrates, and stop the operation when the saw program of the equipment doesn't match the expected fiducial design on the substrate. These unique fiducial marks provide an error free solution that prevents loading wrong saw programs or feeding incorrect CSP substrates/packages into the saw singulation equipment. The benefits are that different type and sizes of CSP packages will not be sawn with the wrong dimensions, and that expensive saw singulation equipment parts will not get damaged.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129692399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}