IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.最新文献

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Validating and characterizing high speed datacom devices 验证和表征高速数据通信设备
T. Napier
{"title":"Validating and characterizing high speed datacom devices","authors":"T. Napier","doi":"10.1109/IEMT.2003.1225904","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225904","url":null,"abstract":"ICs developed for data communications present a number of challenges in the development of test solutions to be used in validation, characterization, and high volume production. One of the most obvious challenges is the frequency and data rates at which these devices operate. The OC-48 standard in use today transmits and receives data at 2.5 Gbps. Emerging standards of \"Xaui\" and \"OC-192\" operate at 3.2 Gbps and 9.6 Gbps respectively, which provide even greater challenges. The majority of ATE today operates at /spl Lt/1 Gbps. A few ATE companies have announced solutions that will be able to provide at 3.2 Gbps, but these solutions are hard to find. Other challenges are jitter requirements as low as 5pS, non-deterministic data delays in the devices, signal pin counts above 500 pins, and low voltage differential swings. This paper looks at these challenges and solutions. The results from OC-48, Xaui, and OC-192 projects developed by NPTest SABER will be presented. These solutions use a combination of ATE, external instrumentation, custom interfacing, and software. The paper will also look at tradeoffs in these solutions.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129540499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new wafer level package for improved electrical and reliability performance 一个新的晶圆级封装,提高电气和可靠性性能
S. Barrett, J. Reche, Deok-Hoon Kim, D. Stepniak
{"title":"A new wafer level package for improved electrical and reliability performance","authors":"S. Barrett, J. Reche, Deok-Hoon Kim, D. Stepniak","doi":"10.1109/IEMT.2003.1225893","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225893","url":null,"abstract":"Wafer level packages (WLPs) have demonstrated a very clear size and cost advantage vs. traditional wirebond technologies, especially for small components that have a high number of dice and I/O per wafer. The Kulicke & Soffa Flip Chip Division (FCD) introduced it's first WLP in 1998. This initial WLP utilized a bump on nitride structure (BON) which had good reliability but also high input capacitance. A new WLP has been developed by FCD. This new WLP has a solder bump on polymer (BOP) dielectric structure. A major driver for pursuing a BOP structure was to achieve minimal input capacitance for high speed applications. During development, a new polymer dielectric material was carefully selected based on reliability tests and manufacturability. Thermal Cycling (TC) test showed 30% better TC performance vs. the BON structure. The new WLP also passed 168 hours of autoclave and JEDEC Level 1 Preconditioning testing. In this paper, the advantages of this new WLP will be discussed in detail. In addition, reliability test results will be presented.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115379951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A novel gold deposition process for wafer applications 一种新的晶圆金沉积工艺
N. Brown, E. Douglass
{"title":"A novel gold deposition process for wafer applications","authors":"N. Brown, E. Douglass","doi":"10.1109/IEMT.2003.1225921","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225921","url":null,"abstract":"The deposition of nickel and gold layers as under bump metallurgy (UBM) for wafer bump applications has been established as a viable means of ensuring adhesion and bond reliability. These nickel/gold layers can be used in subsequent processes that employ either wire bonding directly to die pads or screened and reflowed solder paste for connectivity to next level substrates. This paper will discuss the process chemistries used to produce nickel/gold metallurgies over copper or aluminum die pads. Conventional immersion gold processes deposit gold from solution via a displacement reaction with the surface of the nickel layer. This reaction continues until the gold completely covers any available nickel sites. This mechanism, therefore, limits the possible thicknesses obtainable from immersion gold processes to about 0.10-0.15 microns. A new gold deposition process will be described that operates in a similar way but is not limited by the displacement mechanism. This chemistry is capable of depositing significantly higher thicknesses of gold over nickel substrates, thus allowing this technology to be used for many new applications that normally would require electrolytic deposition of gold. The advantages of using an 'immersion' process are it's ability to deposit very uniform deposit thicknesses across a wafer surface, no requirement for electrical continuity across the plateable surface and the practicality of processing a large number of wafers at one time. Performance results and operating characteristics of the new gold process will be reviewed. Pretreatment processes necessary to ensure optimum reliability will also be discussed.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116356553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The challenge of testing ultra fine pitch wire bonds 测试超细间距金属键的挑战
R. Sykes
{"title":"The challenge of testing ultra fine pitch wire bonds","authors":"R. Sykes","doi":"10.1109/IEMT.2003.1225876","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225876","url":null,"abstract":"History and industrial road maps clearly show an ever-decreasing pitch between wire bonds. Until recently, the challenges of meeting this demand have fallen on other processes more than the science of bond testing. With industrial bonding at 50 /spl mu/m becoming common place, this is no longer the case. Wire bonding at 25 /spl mu/m and below is proven in laboratories, including the shear and pull testing of these wires. Although it is possible to use existing testers at these geometry's their ease of use and accuracy is being pushed to, if not beyond, their limits.Ultra Fine Pitch wire bonding is proposed as the next generation bond tester to meet the growing demand.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128776268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A methodology for the generation of dynamic compact models of packages and heat sinks from thermal transient measurements 从热瞬态测量中生成封装和散热器的动态紧凑模型的方法
M. Rencz, G. Farkas, A. Poppe, V. Székely, B. Courtois
{"title":"A methodology for the generation of dynamic compact models of packages and heat sinks from thermal transient measurements","authors":"M. Rencz, G. Farkas, A. Poppe, V. Székely, B. Courtois","doi":"10.1109/IEMT.2003.1225887","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225887","url":null,"abstract":"In this paper we present a methodology that we have recently elaborated for the generation of transient compact models of packages and heat sinks entirely from measured thermal transient results. The main advantage of generating the models from measured results is the time-gain. We do not need to build up the detailed structural model of the package or the heat sink in order to simulate it, as suggested by the DELPHI methodology. An additional advantage is that the lengthy transient simulations are not needed. In the paper we first summarize the way of generating the compact models of packages and heat sinks from measurements. After this we present how to use the obtained dynamic compact package models in board level simulators, that are extended with the feature of calculating with compact models.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128915031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Customer driven innovation process 客户驱动的创新过程
R. Pennisi, G. Kim
{"title":"Customer driven innovation process","authors":"R. Pennisi, G. Kim","doi":"10.1109/IEMT.2003.1225925","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225925","url":null,"abstract":"In order to drive improvements in the product development process and reduce time to market it is essential that the emerging technologies be sufficiently understood prior to product commitment. Today's leaner technology development teams are challenged not only to predict which of the many potential ideas will create killer products, but also insure that they are ready for product introduction. Increasing global competition and the rapid availability of information has decreased the window to evaluate potential options and tradeoffs, select the best solution and then implement the solution that enables the company to take advantage of a market opportunity. Companies with structured processes that enable teams to identify and focus on customer-valued innovations and rapidly drive them to commercialization will emerge as the market leaders. Outcome-based market research techniques were used to identify the criteria that engineering and business teams use to judge the value of new technologies. From this research, a technology maturity process was developed and implemented that selects which emerging technologies would create customer value, identifies the potential tradeoffs against program constraints, and drives the development of these technologies to meet the product and supply chain requirements.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124755944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High reliability BGA package improvements on module total cost of ownership 高可靠性BGA封装改进模块总拥有成本
D. Alcoe, K. Blackwell, R. Rai
{"title":"High reliability BGA package improvements on module total cost of ownership","authors":"D. Alcoe, K. Blackwell, R. Rai","doi":"10.1109/IEMT.2003.1225914","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225914","url":null,"abstract":"This paper describes mechanical reliability and relative cost comparisons from the system ownership point of view. Total system cost performance of a PTFE based organic ball grid array chip package is compared, on a relative basis, to that obtained with other BGA packages having organic as well as ceramic technologies. Mechanical reliability performance values obtained in common reliability testing are projected to field usage performance, and compared across these various package types. The paper discusses the results for large body sizes and large die sizes, where interesting trends are noted. Considering the various package types and sizes, this study identifies primary assembly (to printed wiring board) costs, on a relative basis, including standard BGA assembly, land grid array with sockets, and column grid array. Combining this assembly data with package reliability projections, a simple guide is provided for the total cost of ownership over a period of time. Further refinement, including system availability and service costs, is discussed.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124587986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Modeling and simulation of 12.5 Gb/s on a HyperBGA/sup /spl reg// package 在HyperBGA/sup /spl reg//封装上12.5 Gb/s的建模与仿真
R.D. McBride, S. Rosser, R. P. Nowak
{"title":"Modeling and simulation of 12.5 Gb/s on a HyperBGA/sup /spl reg// package","authors":"R.D. McBride, S. Rosser, R. P. Nowak","doi":"10.1109/IEMT.2003.1225891","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225891","url":null,"abstract":"This paper presents high-speed/high-frequency modeling and simulation results for Endicott Interconnect Technologies' HyperBGA/sup /spl reg// organic chip-carrier package. Utilizing industry leading advanced software tools, Ansoft Links/sup TM/, Ansoft HFSS/sup TM/, and Ansoft Serenade/sup /spl reg//, this modeling and simulation effort has demonstrated that current HyperBGA/sup /spl reg// technology will meet the performance requirements for applications running at speeds of 12.5 Gb/s per channel. Throughout the course of this discussion, the general modeling and simulation methodology is revealed, along with the actual physical structures modeled and the inherent assumptions and boundary conditions involved.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"614 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123044961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
An acoustic sensor for monitoring microelectronics packaging manufacturing processes 一种用于监测微电子封装制造过程的声学传感器
F. Williams, S. Pinkett, W. Hunt, G. May
{"title":"An acoustic sensor for monitoring microelectronics packaging manufacturing processes","authors":"F. Williams, S. Pinkett, W. Hunt, G. May","doi":"10.1109/IEMT.2003.1225873","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225873","url":null,"abstract":"Since microelectronics fabrication processes require numerous steps, cost and yield are critical concerns. In-situ monitoring is vital for process control. However, this goal is restricted by the shortage of available sensors capable of performing in this manner. This paper proposes a silicon acoustic sensor to be used for in-situ monitoring of electrochemical or plasma deposition processes. The sensor was fabricated using common integrated circuit (IC) and micromachining techniques. Such techniques enable the creation of extremely thin beams and membranes, thus enabling devices to be highly sensitive to a measurand such as pressure. The sensing element of the microphone is a deflectable thin diaphragm composed of silicon and a piezoelectric material, zinc oxide (ZnO). The transduction operation is based on the piezoelectric effect, where a mechanical pressure applied to a polarized ZnO crystal results in a mechanical deformation. This resulting strain induces an electrical charge on the ZnO surface. To collect these surface charges on the sensor optimally, we implement segmented electrodes in the regions of greatest bending stress. The measured sensitivity of this sensor is 195 /spl mu/V//spl mu/bar.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124556280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Open architecture test system: the new frontier 开放式架构测试系统:新前沿
S. Perez, Y. Furukawa
{"title":"Open architecture test system: the new frontier","authors":"S. Perez, Y. Furukawa","doi":"10.1109/IEMT.2003.1225902","DOIUrl":"https://doi.org/10.1109/IEMT.2003.1225902","url":null,"abstract":"The recent test challenges have resulted ina general consensus that the test industry needs a fundamental change. The increasing complexity of the present day System-on-a-Chip (SOC) devices and simultaneous demand in the test cost reduction has forced both IC manufactures (ATE End Users) and tester vendors (ATE Suppliers) to re-think how IC testing should be done. According to the 2001 ITRS roadmap, without re-engineering, the projected tester cost will continue to increase in the near future; such increasing cost alone requires a fundamental change. A common, open architecture test system platform has been envisioned to address this challenge. The open architecture allows third parties to develop test solutions in the most efficient environment and promotes the reusability of hardware and software modules. Thus, it reduces the development time (time to market) and the overall testing cost. This paper discusses the basic concept of the Semiconductor Test Consortium open architecture (OPEN STAR/sup TM/) together with the benefits to the industry and the program to implement this industry wide effort.","PeriodicalId":106415,"journal":{"name":"IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120964850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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